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PDF LM89 Data sheet ( Hoja de datos )
| Número de pieza | LM89 | |
| Descripción | 0.75C Accurate / Remote Diode and Local Digital Temperature Sensor with Two-Wire Interface | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 2004
LM89
±0.75˚C Accurate, Remote Diode and Local Digital
Temperature Sensor with Two-Wire Interface
General Description
The LM89 is an 11-bit digital temperature sensor with a
2-wire System Management Bus (SMBus) serial interface.
The LM89 accurately measures its own temperature as well
as the temperature of an external device, such as processor
thermal diode or diode-connected transistor such as the
2N3904. The temperature of any ASIC can be accurately
determined using the LM89 as long as a dedicated diode
(semiconductor junction) is available on the target die. The
LM89 remote sensor accuracy of ±0.75˚C is factory trimmed
for the series resistance and 1.0021 typical non-ideality fac-
tor of the Intel® Pentium™ 4 and the Mobile Pentium 4
Processor-M thermal diode. The LM89 has an Offset
register to allow measuring other diodes without
requiring continuous software management. Contact
hardware.monitor.team@nsc.com to obtain the latest data for
new processors.
The LM89 and the LM89-1 have the same functions but
different SMBus slave addresses. This allows for one of
each to be on the bus at the same time.
Activation of the ALERT output occurs when any tempera-
ture goes outside a preprogrammed window set by the HIGH
and LOW temperature limit registers or exceeds the T_CRIT
temperature limit. Activation of the T_CRIT_A occurs when
any temperature exceeds the T_CRIT programmed limit.
The LM89 is pin and register compatible with the LM86,
LM90, Analog Devices ADM1032 and Maxim MAX6657/8.
Features
n Accurately senses die temperature of remote ICs or
diode junctions
n Offset register allows sensing a variety of thermal
diodes accurately
n On-board local temperature sensing
n 10 bit plus sign remote diode temperature data format,
0.125 ˚C resolution
n T_CRIT_A output useful for system shutdown
n ALERT output supports SMBus 2.0 protocol
n SMBus 2.0 compatible interface, supports TIMEOUT
n 8-pin MSOP and SOIC packages
Key Specifications
j Supply Voltage
3.0 V to 3.6 V
j Supply Current
0.8 mA (typ)
j Local Temp Accuracy (includes quantization error)
TA=25˚C to 125˚C ±3.0 ˚C (max)
j Remote Diode Temp Accuracy (includes quantization
error)
TA=30˚C,TD=80˚C
TA=30˚C to 50˚C, TD=60˚C to 100˚C
TA=0˚C to 85˚C, TD=25˚C to 125˚C
±0.75 ˚C (max)
±1.0 ˚C (max)
±3.0 ˚C (max)
Applications
n Processor/Computer System Thermal Management
(e.g. Laptop, Desktop, Workstations, Server)
n Electronic Test Equipment
n Office Electronics
Simplified Block Diagram
Pentium™ is a trademark of Intel Corporation.
© 2004 National Semiconductor Corporation DS200415
20041501
www.national.com
1 page  
Temperature-to-Digital Converter Characteristics (Continued)
Unless otherwise noted, these specifications apply for VDD=+3.0Vdc to 3.6Vdc. Boldface limits apply for TA = TJ =
TMIN≤TA≤TMAX; all other limits TA= TJ=+25˚C, unless otherwise noted.
Parameter
Conditions
Typical
Limits
Units
(Note 6)
(Note 7)
(Limit)
Remote T_CRIT Default Temperature Setting (Note 11)
+110
˚C
Logic Electrical Characteristics
DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for VDD=+3.0 to 3.6 Vdc. Boldface lim-
its apply for TA = TJ = TMIN to TMAX; all other limits TA= TJ=+25˚C, unless otherwise noted.
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 6)
(Note 7)
(Limit)
SMBData, SMBCLK INPUTS
VIN(1)
VIN(0)
VIN(HYST)
Logical “1” Input Voltage
Logical “0”Input Voltage
SMBData and SMBCLK Digital
Input Hysteresis
IIN(1)
Logical “1” Input Current
IIN(0)
Logical “0” Input Current
CIN Input Capacitance
ALL DIGITAL OUTPUTS
VIN = VDD
VIN = 0 V
400
0.005
−0.005
5
2.1 V (min)
0.8 V (max)
mV
±10 µA (max)
±10 µA (max)
pF
IOH
High Level Output Current
VOH = VDD
10 µA (max)
VOL SMBus Low Level Output Voltage IOL = 4mA
0.4 V (max)
IOL = 6mA
0.6
SMBus DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for VDD=+3.0 Vdc to
+3.6 Vdc, CL (load capacitance) on output lines = 80 pF. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits
TA = TJ = +25˚C, unless otherwise noted. The switching characteristics of the LM89 fully meet or exceed the published specifi-
cations of the SMBus version 2.0. The following parameters are the timing relationships between SMBCLK and SMBData sig-
nals related to the LM89. They adhere to but are not necessarily the SMBus bus specifications.
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 6)
(Note 7)
(Limit)
fSMB
SMBus Clock Frequency
100 kHz (max)
10 kHz (min)
tLOW
SMBus Clock Low Time
tHIGH
tR,SMB
tF,SMB
tOF
SMBus Clock High Time
SMBus Rise Time
SMBus Fall Time
Output Fall Time
tTIMEOUT
SMBData and SMBCLK Time Low for
Reset of Serial Interface (Note 14)
from VIN(0)max to
VIN(0)max
from VIN(1)min to VIN(1)min
(Note 12)
(Note 13)
CL = 400pF,
IO = 3mA, (Note 13)
1
0.3
4.7 µs (min)
25 ms (max)
4.0 µs (min)
µs (max)
µs (max)
250 ns (max)
25 ms (min)
35 ms (max)
tSU;DAT
tHD;DAT
Data In Setup Time to SMBCLK High
Data Out Stable after SMBCLK Low
250 ns (min)
300 ns (min)
900 ns (max)
tHD;STA
Start Condition SMBData Low to SMBCLK
Low (Start condition hold before the first
clock falling edge)
100 ns (min)
tSU;STO
Stop Condition SMBCLK High to SMBData
Low (Stop Condition Setup)
100 ns (min)
tSU;STA
SMBus Repeated Start-Condition Setup
Time, SMBCLK High to SMBData Low
0.6 µs (min)
tBUF SMBus Free Time Between Stop and Start
Conditions
1.3 µs (min)
5 www.national.com
5 Page 
1.0 Functional Description (Continued)
1.9.1 SMBus Timing Diagrams
LM89 Timing Diagram
20041510
(a) Serial Bus Write to the internal Command Register followed by a the Data Byte
(b) Serial Bus Write to the Internal Command Register
20041511
20041512
(c) Serial Bus Read from a Register with the Internal Command Register preset to desired value.
FIGURE 7. SMBus Timing Diagrams
1.10 SERIAL INTERFACE RESET
In the event that the SMBus Master is RESET while the
LM89 is transmitting on the SMBData line, the LM89 must be
returned to a known state in the communication protocol.
This may be done in one of two ways:
1. When SMBData is LOW, the LM89 SMBus state ma-
chine resets to the SMBus idle state if either SMBData
or SMBCLK are held low for more than 35ms (tTIMEOUT).
Note that according to SMBus specification 2.0 all de-
vices are to timeout when either the SMBCLK or SMB-
Data lines are held low for 25-35ms. Therefore, to insure
a timeout of all devices on the bus the SMBCLK or
SMBData lines must be held low for at least 35ms.
2. When SMBData is HIGH, have the master initiate an
SMBus start. The LM89 will respond properly to an
SMBus start condition at any point during the communi-
cation. After the start the LM89 will expect an SMBus
Address address byte.
1.11 DIGITAL FILTER
In order to suppress erroneous remote temperature readings
due to noise, the LM89 incorporates a user-configured digital
filter. The filter is accessed in the FILTER and ALERT CON-
11 www.national.com
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LM89.PDF ] | |
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