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PDF TDA1549T Data sheet ( Hoja de datos )
| Número de pieza | TDA1549T | |
| Descripción | Stereo 4fs data input up-sampling filter with bitstream continuous calibration DAC BCC-DAC1 | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA1549T
Stereo 4fs data input up-sampling
filter with bitstream continuous
calibration DAC (BCC-DAC1)
Objective specification
File under Integrated Circuits, IC01
August 1994
Philips Semiconductors
1 page  
Philips Semiconductors
Stereo 4fs data input up-sampling filter with
bitstream continuous calibration DAC (BCC-DAC1)
Objective specification
TDA1549T
PINNING
SYMBOL PIN
DESCRIPTION
WS 1 word select input
BCK
2 bit clock input
TEST
3 test input; pin should be connected to
ground
VOL
4 left channel output
FILTCL
5 capacitor for left channel 1st order
filter function; should be connected
between pins 4 and 5
FILTCR
6 capacitor for right channel 1st order
filter function; should be connected
between pins 6 and 7
VOR
7 right channel output
Vref
VSSO
VDDO
VDDA
VSSA
n.c.
8 internal reference voltage for output
channels (1⁄2VDD)
9 operational amplifier ground
10 operational amplifier supply voltage
11 analog supply voltage
12 analog ground
13 not connected (this pin should be left
open-circuit)
VSSD
VDDD
DATA
14 digital ground
15 digital supply voltage
16 data input
Fig.2 Pin configuration.
August 1994
5
5 Page 
Philips Semiconductors
Stereo 4fs data input up-sampling filter with
bitstream continuous calibration DAC (BCC-DAC1)
Objective specification
TDA1549T
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Reference values
Vref
RCONV
reference voltage level
current-to-voltage conversion
resistance
2.45 2.5
1.6 2.2
2.55 V
2.8 kΩ
Analog outputs; pins VOL and VOR
RES
resolution
−−
18 bit
VFS(rms)
VOFF
TCFS
(THD + N)/S
full-scale output voltage (RMS value)
output voltage DC offset with respect
to reference voltage level Vref
full-scale temperature coefficient
total harmonic distortion plus
noise-to-signal ratio
at 0 dB input level;
note 6
1.425 1.5
−80 −65
1.575
−50
− ±100 x 10−6 −
− −90
−83
− 0.003 0.007
V
mV
dB
%
at −60 dB input level;
note 7
at −60 dB input level;
A-weighted; note 8
−
−
−
−
−48
0.40
−50
0.32
−40 dB
1.0 %
− dB
−%
at 0 dB input level;
20 Hz to 20 kHz;
note 9
−
−
−90
0.003
−83
0.007
dB
%
S/N signal-to-noise ratio at bipolar zero A-weighted;
100 110 − dB
at code 00000H
tcs
αcs
|∆VO|
|ZO|
RL
CL
current setting time to ±1 LSB
channel separation
unbalance between outputs
dynamic output impedance
output load resistance
output load capacitance
− 0.1
85 100
− 0.2
− 10
3−
−−
− ms
− dB
0.3 dB
−W
− kΩ
200 pF
Notes
1. All VDD and VSS pins must be connected externally to the same supply.
2. Measured with VDDD = VDDA = VDDO = 5 V at input data code 00000H.
3. Measured with VDDD = VDDA = VDDO = 3.8 V at input data code 00000H.
4. Vripple = 1% of the supply voltage and fripple = 100 Hz. Ripple rejection RR to VDDA is dependent on the value of the
external capacitor (CEXT3 in Fig.1) connected to Vref. The value quoted here assumes CEXT3 = 1 µF.
5. Around multiples of 4fs.
6. Measured with a 1 kHz, 0 dB, 18-bit sine wave generated at a sampling rate of 192 kHz.
(THD + N)/S measured over a bandwidth from 20 Hz to 20 kHz.
7. Measured with a 1 kHz, −60 dB, 18-bit sine wave generated at a sampling rate of 192 kHz. (THD + N)/S measured
over a bandwidth from 20 Hz to 20 kHz.
8. Measured with a 1 kHz, −60 dB, 18-bit sine wave generated at a sampling rate of 192 kHz.
(THD + N)/S measured over a bandwidth from 20 Hz to 20 kHz and filtered with A-weighted characteristic.
9. Measured with a 0 dB, 18-bit sine wave from 20 Hz to 20 kHz generated at a sampling rate of 192 kHz. (THD + N)/S
measured over a bandwidth from 20 Hz to 20 kHz.
August 1994
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet TDA1549T.PDF ] | |
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