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PDF UPD30121F1-131-GA1 Data sheet ( Hoja de datos )
| Número de pieza | UPD30121F1-131-GA1 | |
| Descripción | VR4121TM 64-/32-BIT MICROPROCESSOR | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30121
VR4121TM
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The µPD30121 (VR4121) is one of NEC’s VR SeriesTM RISC (Reduced Instruction Set Computer) microprocessors
and is a high-performance 64-/32-bit microprocessor employing the MIPSTM RISC architecture.
The VR4121 uses the high-performance, super power-saving VR4120TM as the CPU core, and has many peripheral
functions such as a DMA controller, software modem interface, serial interface, keyboard interface, IrDA interface,
touch panel interface, real-time clock, A/D converter, and D/A converter. Configured with these functions, the
VR4121 is suitable for high-speed battery-driven portable information systems. The external memory bus width can
be selected from 32 bits and 16 bits, realizing high-speed data transfer.
Detailed function descriptions are provided in the following user’s manual. Be sure to read it before
designing.
• VR4121 User’s Manual (U13569E)
FEATURES
• Employs 64-bit MIPS architecture
• Conforms to MIPS III instruction set (deleting FPU,
LL, LLD, SC, and SCD instructions)
• Optimized 6-stage pipeline
• Supports MIPS16 instruction set
• Supports high-speed product-sum operation
instructions
• Supports four types of operating modes, enabling
more effective power-consumption management
• Internal maximum operating frequency: 131/168 MHz
• On-chip clock generator
• Address space physical: 32 bits
virtual: 40 bits
Integrates 32 double entry TLBs
• High-capacity instruction/data separated cache
memories
Instruction: 16 Kbytes
Data:
8 Kbytes
• Memory controller (ROM, EDO-type DRAM,
synchronous DRAM (SDRAM), synchronous ROM
(SROM), and flash memory supported)
• Keyboard interface and touch panel interface
• 4-channel DMA controller
• Serial interface (NS16550 compatible)
• IrDA interface for infrared communication
• Software modem interface
• A/D and D/A converters to support digital voice I/O
• Supports ISA bus subset
• Power supply voltage: VDD2 = 2.5 V (internal), VDD3 =
3.3 V (external) (131 MHz model)
• Package: 224-pin fine-pitch FBGA
APPLICATIONS
• Battery-driven portable information systems
• Embedded controllers, etc.
ORDERING INFORMATION
Part Number
µPD30121F1-131-GA1
µPD30121F1-168-GA1
Package
224-pin plastic FBGA (16 × 16)
224-pin plastic FBGA (16 × 16)
Internal Maximum Operating Frequency
131 MHz
168 MHz
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14691EJ1V0DS00 (1st edition)
Date Published June 2000 N CP(K)
Printed in Japan
©
2000
1 page  
µPD30121
PIN IDENTIFICATION
ADD (0:25):
ADIN (0:2):
AFERST#:
AGND:
AUDIOIN:
AUDIOOUT:
AVDD:
BATTINH:
BATTINT#:
BUSCLK:
CGND:
CKE:
CLKSEL (0:2):
CLKX1:
CLKX2:
CTS#:
CVDD:
DATA (0:31):
DBUS32:
DCD#:
DCTS#:
DDIN:
DDOUT:
DGND:
DRTS#:
DSR#:
DTR#:
DVDD:
FIRCLK:
FIRDIN#:
FS:
GND2, GND3:
GNDP, GNDPD:
GPIO (0:49):
HC0:
HLDACK#:
HLDRQ#:
HSPMCLK:
HSPSCLK:
ILCSENSE:
IOCHRDY:
IOCS16#:
IOR#:
IOW#:
IRDIN:
IRDOUT#:
IRING:
KPORT (0:7):
KSCAN (0:11):
LCAS#:
Address Bus
General Purpose Input for A/D
AFE Reset
GND for A/D
Audio Input
Audio Output
VDD for A/D
Battery Inhibit
Battery Interrupt Request
System Bus Clock
GND for Oscillator
Clock Enable
Clock Select
Clock X1
Clock X2
Clear to Send
VDD for Oscillator
Data Bus
Data Bus 32
Data Carrier Detect
Debug Serial Clear to Send
Debug Serial Data Input
Debug Serial Data Output
GND for D/A
Debug Serial Request to Send
Data Set Ready
Data Terminal Ready
VDD for D/A
FIR Clock
FIR Data Input
Frame Synchronization
Ground
Ground for PLL
General Purpose I/O
Hardware Control 0
Hold Acknowledge
Hold Request
HSP Codec Master Clock
HSP Codec Serial Clock
Input Loop Current Sensing
I/O Channel Ready
I/O Chip Select 16
I/O Read
I/O Write
IrDA Data Input
IrDA Data Output
Input Ring
Key Code Data Input
Key Scan Line
Lower Column Address Strobe
Remark # indicates active low.
LCDCS#:
LCDRDY:
LEDOUT#:
MEMCS16#:
MEMR#:
MEMW#:
MIPS16EN:
MPOWER:
MRAS(0:3)#:
MUTE:
OFFHOOK:
OPD#:
PIUGND:
PIUVDD:
POWER:
POWERON:
RD#:
ROMCS(0:3)#:
RSTOUT:
RSTSW#:
RTCRST#:
RTCX1:
RTCX2:
RTS#:
RxD:
SCAS#:
SCLK:
SDI:
SDO:
SEL:
SHB#:
SMODE (1:2):
SPOWER:
SRAS#:
SYSDIR:
TELCON:
TPX (0:1):
TPY (0:1):
TxD:
UCAS#:
ULCAS#:
UUCAS#:
VDD2, VDD3:
VDDP, VDDPD:
WR#:
ZWS#:
LCD Chip Select
LCD Ready
LED Output
Memory Chip Select 16
Memory Read
Memory Write
MIPS16 Enable
Main Power
DRAM Row Address Strobe
Mute
Off Hook
Output Power Down
GND for Touch Panel Interface
VDD for Touch Panel Interface
Power Switch
Power On State
Read
ROM Chip Select
System Bus Reset Output
Reset Switch
Real-time Clock Reset
Real-time Clock X1
Real-time Clock X2
Request to Send
Receive Data
Column Address Strobe for
SDRAM/SROM
SDRAM/SROM Clock
HSP Serial Data Input
HSP Serial Data Output
IrDA Module Select
System Hi-Byte Enable
SDRAM Mode
SDRAM Power Control
Row Address Strobe for
SDRAM/SROM
System Bus Buffer Direction
Telephone Control
Touch Panel X I/O
Touch Panel Y I/O
Transmit Data
Upper Column Address Strobe
Lower Byte of Upper Column
Address Strobe
Upper Byte of Upper Column
Address Strobe
Power Supply Voltage
VDD for PLL
Write
Zero Wait State
Data Sheet U14691EJ1V0DS00
5
5 Page 
µPD30121
(3) Battery monitor interface signals
Signal
BATTINH/
BATTINT#
I/O Function
I This function differs depending on how the MPOWER signal is set.
<When MPOWER signal = 0>
BATTINH function
This signal enables/prohibits activation due to power-on.
1 : Enable activation
0 : Prohibit activation
<When MPOWER signal = 1>
BATTINT# function
This is an interrupt signal that is output when remaining power is low during normal operations. The
external agent checks the remaining battery power. Activate the signal at this pin if voltage sufficient
for operations cannot be supplied.
(4) Initialization interface signals
Signal
MPOWER
POWERON
POWER
RSTSW#
RTCRST#
I/O Function
O This signal indicates the VR4121 is operating. This signal is inactive during Hibernate mode.
O This signal indicates the VR4121 is ready to operate. It becomes active when a power-on factor is
detected and becomes inactive when the BATTINH/BATTINT# signal check operation is completed.
I This is a VR4121 activation signal.
I This is a VR4121 reset signal.
I This signal resets RTC. When power is first supplied to a device, the external agent must assert the
signal at this pin for about 2 s.
Data Sheet U14691EJ1V0DS00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD30121F1-131-GA1.PDF ] | |
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