UPD2845GR Datasheet PDF - NEC
Part Number | UPD2845GR | |
Description | 1 V/ 1.3 mA/ 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM | |
Manufacturers | NEC | |
Logo | ||
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CMOS DIGITAL INTEGRATED CIRCUITS
PPD2845GR
1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI
FOR PAGER SYSTEM
DESCRIPTION
PPD2845GR is a PLL synthesizer LSI for pager system. This LSI is manufactured using low voltage CMOS
process and therefore realized the low power consumption PLL operated on 1 V, 1.3 mA. This LSI is packaged in 16
pin plastic SSOP suitable for high-density surface mounting. So, this product contributes to produce a long-life-
battery and physically-small pager system.
FEATURES
• Operating frequency : · Input frequency : fin = 10 MHz to 94 MHz
· Reference oscillating frequency : fx’tal = 12.8 MHz
• Low Supply voltage : · PLL block : VDD1 = 1.00 V to 1.15 V @ fin = 10 MHz to 70 MHz
VDD1 = 1.05 V to 1.15 V @ fin = 10 MHz to 94 MHz
· Charge pump block: VDD2 = 3.0 V ± 300 mV
• Low power consumption • IDD = 1.3 mA TYP. @ fin = 70 MHz, fx’tal = 12.8 MHz
• Equipped with power-save function • Serial data can be received in power-save mode.
• Packaged in 16 pin plastic SSOP suitable for high-density surface mounting.
ORDERING INFORMATION
PART NUMBER
PPD2845GR-E1
PPD2845GR-E2
PACKAGE
16 pin plastic SSOP
(225 mil)
16 pin plastic SSOP
(225 mil)
SUPPLYING FORM
Embossed tape 12 mm wide. QTY 2.5 k/reel
Pin 1 is in tape pull-out direction.
Embossed tape 12 mm wide. QTY 2.5 k/reel
Pin 1 is in tape roll-in direction.
* To order evaluation samples, please contact your local NEC sales office (Order number : PPD2845GR).
PIN ASSIGNMENT
(Top View)
VDD1
XI
FIN XO
GND
LE
FR CLK
RESET
DATA
EO PS
EOP
NC
EON
VDD2
Caution Electro-static sensitive devices
Document No. P12150EJ2V0DS00 (2nd edition)
(Previous No. IC-3291)
Date Published February 1997 N
Pi di J
© 1994
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PPD2845GR
ELECTRICAL CHARACTERISTICS
DC PERFORMANCE (Unless otherwise specified, VDD1 = 1.00 V to 1.15 V, VDD2 = 2.70 to 3.30 V, TA = ð10 to +50 °C)
PARAMETER
Supply Voltage
Circuit Current
SYMBOL
VDD1
VDD2
IDD1
MIN.
1.00
2.70
Data Retain Current
High Level Output Current1*1
IDR
IOH1
ð1.0
High Level Output Current2*1
High Level Output Current3*1
Low Level Output Current1*2
IOH2
IOH3
IOL1
ð0.5
ð0.1
1.0
Low Level Output Current2*2
Low Level Output Current3*2
High Level Input Current1*2
Low Level Input Current1*1
High Level Input Current2*2
IOL2
IOL3
IIH1
IIL1
IIH2
0.4
0.4
0.4
ð0.4
High Level Input Voltage1
VIH1
0.8 u VDD1
Low Level Input Voltage1
VIL1
0
High Level Input Voltage2
VIH2
0.8 u VDD1
Low Level Input Voltage2
VIL2
0
Output Leak Current
IL
*1 Current from IC
*2 Current into IC
TYP.
1.05
3.0
1.3
1.0
10ð4
MAX.
1.15
3.30
2.2
10
1.0
4.0
0.2 u VDD1
VDD1
0.2 u VDD1
r1.0
UNIT
V
V
mA
PA
mA
mA
mA
mA
mA
mA
PA
PA
PA
V
V
V
V
PA
CONDITIONS
PLL Operation
P/D Charge pump block
fin = 70 MHz, 0.2 VP-P.
fx’tal = 12.8 MHz X’tal OSC IN.
VDD1 = 1.0 V to 1.1 V
VDD2 = 2.85 V to 3.15 V
No Input Signal, VDD1 = 1.1 V
EO, EOP pin. VDD2 = 2.85 V
VOH = VDD2 ð0.5 V
XO pin. VOH = VDD1 ð0.5 V
FR pin. VOH = VDD1 ð0.5 V
EO, EON pin. VDD2 = 2.85 V
VOL = 0.5 V
XO pin. VOL = 0.5 V
FR pin. VOL = 0.5 V
FIN, XI pin. VIH = VDD1 1.0 V
FIN, XI pin. VIL = 0 V, VDD1 1.0 V
DATA, CLK, LE, PS pin. VIH1 = 3.85 V
DATA, CLK, LE, PS pin.
DATA, CLK, LE, PS pin.
RESET pin.
RESET pin.
EO, EOP, EON pin.
VDD1 = 1.0 V to 1.1 V
VDD2 = 2.85 V to 3.15 V
AC PERFORMANCE (Unless otherwise specified, VDD1 = 1.00 V to 1.15 V, VDD2 = 2.70 to 3.30 V, TA = ð10 to +50 qC)
PARAMETER
Input frequency 1
Input frequency 2
SYMBOL
fin1
fin2
MIN.
10
10
Reference Oscillating Frequency
fx’tal
TYP.
12.8
MAX.
70
94
UNIT
MHz
MHz
MHz
CONDITIONS
FIN pin, Vin = 0.2 VP-P
FIN pin, Vin = 0.2 VP-P,
VDD1 = 1.05 V to 1.15 V
XI, XO pin
5
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Information | Total 16 Pages | |
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