PDF UMA1022M Data sheet ( Hoja de datos )

Número de pieza	UMA1022M
Descripción	Low cost dual frequency synthesizer for radio telephones
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET UMA1022M Low cost dual frequency synthesizer for radio telephones Product speciﬁcation Supersedes data of 1998 May 15 File under Integrated Circuits, IC17 1998 Dec 09 1 page Philips Semiconductors Low cost dual frequency synthesizer for radio telephones Product speciﬁcation UMA1022M FUNCTIONAL DESCRIPTION Main dividers The main dividers are clocked at pin RFA by the RF oscillator signal and at pin IFB by the IF oscillator signal. The inputs are AC coupled through external capacitors. Input impedances are high, dominated by parasitic package capacitances, so matching is off-chip. The sensitive dividers operate with signal levels from 35 to 225 mV (RMS), at frequencies up to 2.1 GHz (RF part) and up to 550 MHz (IF part). Both include programmable bipolar prescalers followed by CMOS counters. The RF main divider allows programmable ratios from 512 to 65535; the IF blocks accept values between 128 and 16383. Crystal oscillator A fully differential low-noise amplifier/buffer is integrated providing outputs to drive other circuits, and to build a crystal oscillator; only needed are an external resonance circuit and tuning elements (temperature compensation). A bus controlled power-down mode disables the low-noise amplifier to reduce current if not needed. The normal differential input pins drive a clock buffer to provide edges to the programmable reference divider at frequencies up to 20 MHz. The inputs are AC coupled through external capacitors, and operate with signals down to 35 mV (RMS) and up to 0.5 V (RMS). Various crystal oscillator structures can be built using the amplifier. By coupling one output back to the appropriate input through the resonator, and decoupling the other input to ground, the second output becomes available to deliver the reference frequency to other circuits. Reference dividers A first common divider circuit produces an output frequency for RF or IF synthesizer phase comparison, depending on the P/A bit. It drives a second independent divider, which delivers the reference edge to the IF or RF synthesizer phase comparator. When P/A is logic 1, the output of the subdivider is connected to the RF phase comparator, whereas the output of the common divider is connected to the IF phase detector. The phase comparators run at related frequencies with a controlled phase difference to avoid interference when in-lock. The common 10-bit section permits divide ratios from 8 to 1023; the second subdivider allows phase comparison frequency ratios between 1 and 16. Table 2 indicates how to program the corresponding bits to get the wanted ratio. Phase comparators The phase detectors are driven by the output edges selected by the main and reference dividers. Each generates lead and lag signals to control the appropriate charge pump. The pumps output current pulses appear at pins CPA (RF synthesizer) and CPB (IF synthesizer). The current pulse duration is at least equal to the difference in time of arrival of the edges from the two dividers. If the main divider edge arrives first, CPA or CPB sink current. If the reference divider edge arrives first, CPA or CPB source current. For correct PLL operation the VCOs need to have a positive frequency/voltage control slope. The currents at CPA and CPB are programmed via the serial bus as multiples of an internally-set reference current. The passage into power-down mode is synchronized with respect to the phase detector to prevent output current pulses being interrupted. Additional circuitry is included to ensure that the gain of the phase comparators remains linear even for small phase errors. Serial programming bus A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, clock (CLK) and enable (E). The data sent to the device is loaded in bursts framed by E. Programming clock edges and their appropriate data bits are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns HIGH. During normal operation, E should be kept HIGH. Only the last 19 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The NMOS-rich design uses virtually no current when the bus is inactive; power-up is initiated when enable is taken LOW, and power-down occurs a short time after enable returns HIGH. Bus activity is allowed when either synthesizer is active or in power-down (ONA and ONB inputs LOW) mode. Fully static CMOS registers retain programmed data whatever the power-down state, as long as the supply voltage is present. 1998 Dec 09 5 5 Page Philips Semiconductors Low cost dual frequency synthesizer for radio telephones Product speciﬁcation UMA1022M SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Interface logic input signal levels; pins 7, 9, 10, 11 and 13 VIH HIGH-level input voltage VIL LOW-level input voltage Ibias input bias current Ci input capacitance logic 1 or logic 0 0.7VDD −0.3 −5 − Low noise crystal oscillator ampliﬁer output signals; pins 3 and 18 Zo differential output impedance fxtal = 10 MHz − (real part) VXOUT, VXOUTN Gv(diff) Vo(p-p) DC output voltage − small signal differential voltage gain limiting differential output voltage swing (peak-to-peak value) XON = 1; fxtal = 10 MHz 18 XON = 1 − ∆f/f(VDDX) frequency stability as a function of VDDX = 3 V ±5%; note 2 − supply voltage change (referenced to initial frequency) − VDD + 0.3 − 0.3VDD − +5 2− 2− 2.29 − 20 22 2− ±0.25 − V V µA pF kΩ V dB V ppm System speciﬁcation FTRFIF RF frequency and close harmonics feedthrough to IF frequency FTIFRF IF frequency and close harmonics feedthrough to RF frequency note 3 note 3 − 70 − − 50 − dBc dBc Notes 1. Conditions: 0.4 < VCPA < (VCCA − 0.4) and 0.4 < VCPB < (VCCB − 0.4). 2. This value is directly dependent on the external resonator quality factor. Only guaranteed for the application circuit which is given in Fig.5. 3. Only guaranteed on the Philips application board. 1998 Dec 09 11 11 Page

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