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What is CD74HC139M?

This electronic component, produced by the manufacturer "Harris Corporation", performs the same function as "High Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer".


CD74HC139M Datasheet PDF - Harris Corporation

Part Number CD74HC139M
Description High Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer
Manufacturers Harris Corporation 
Logo Harris Corporation Logo 


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SEMICONDUCTOR
September 1997
CD74HC139,
CD74HCT139
High Speed CMOS Logic
Dual 2-to-4 Line Decoder/Demultiplexer
Features
• Multifunction Capability
- Binary to 1 of 4 Decoders or 1 to 4 Line
Demultiplexer
• Active Low Mutually Exclusive Outputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
• Memory Decoding, Data Routing, Code Conversion
Description
The Harris CD74HC139, CD74HCT139 contain two
independent binary to one of four decoders each with a
single active low enable input (1E or 2E). Data on the select
inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four
normally high outputs to go low.
If the enable input is high all four outputs remain high. For
demultiplexer operation the enable input is the data input.
The enable input also functions as a chip select when these
devices are cascaded. This device is functionally the same
as the CD4556B and is pin compatible with it.
The outputs of these devices can drive 10 low power
Schottky TTL equivalent loads. The 74HCT logic family is
functionally as well as pin equivalent to the 74LS logic family.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
PKG.
NO.
CD74HC139E
-55 to 125
16 Ld PDIP E16.3
CD74HCT139E
-55 to 125
16 Ld PDIP E16.3
CD74HC139M
-55 to 125
16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die is available which meets all electrical specifications. Please
contact your local sales office or Harris customer service for
ordering information.
Pinout
CD74HC139, CD74HCT139
(PDIP, SOIC)
TOP VIEW
1E 1
1A0 2
1A1 3
1Y0 4
1Y1 5
1Y2 6
1Y3 7
GND 8
16 VCC
15 2E
14 2A0
13 2A1
12 2Y0
11 2Y1
10 2Y2
9 2Y3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1545.1

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CD74HC139M equivalent
CD74HC139, CD74HCT139
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
VCC
SYMBOL CONDITIONS (V)
25oC
-40oC TO
85oC
MIN TYP MAX MIN MAX
-55oC TO
125oC
MIN MAX UNITS
Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 -
22 ns
6 - - 13 - 16 - 19 ns
Power Dissipation
Capacitance, (Notes 5, 6)
CPD
-
5 - 55 - - - -
- pF
Input Capacitance
HCT TYPES
Propagation Delay
CIN
-
-
- - 10 - 10 -
10 pF
A0, A1 to Outputs
E to Outputs
Select to Output
Enable to Output
Output Transition Time
(Figure 2)
tPLH,
CL = 50pF
4.5
-
- 34 - 43
-
51 ns
tPHL
tPLH,
CL = 50pF
4.5
-
- 34 - 43
-
51 ns
tPHL
tPLH, tPHL CL = 15pF
5
- 14 - - -
-
- ns
tPLH, tPHL CL = 15pF
5
- 14 - - -
-
- ns
tTLH, tTHL CL = 50pF
4.5
-
- 15 - 19
-
22 ns
Power Dissipation
Capacitance, (Notes 5, 6)
CPD
-
5 - 59 - - - -
- pF
Input Capacitance
CIN - - - - 10 - 10
NOTES:
5. CPD is used to determine the dynamic power consumption, per decoder/demux.
6. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
-
10 pF
Test Circuits and Waveforms
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
2.7V
1.3V
0.3V
tf = 6ns
3V
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
1.3V
10%
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5


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