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PDF IDTCSP2510C Data sheet ( Hoja de datos )
| Número de pieza | IDTCSP2510C | |
| Descripción | 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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IDTCSP2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
3.3V PHASE-LOCK LOOP
CLOCK DRIVER
ZERO DELAY BUFFER
0ºC TO 85ºC TEMPERATURE RANGE
IDTCSP2510C
FEATURES:
• Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V VDD
• tpd Phase Error at 133MHz: < ±150ps
• Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz
• Spread Spectrum Compatible
• Operating frequency 25MHz to 140MHz
• Available in 24-Pin TSSOP package
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
11
G
DESCRIPTION:
The CSP2510C is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CSP2510C
operates at 3.3V.
One bank of ten outputs provide low-skew, low-jitter copies of CLK.
Output signal duty cycles are adjusted to 50 percent, independent of the
duty cycle at CLK. The outputs can be enabled or disabled via the control
G input. When the G input is high, the outputs switch in phase and frequency
with CLK; when the G input is low, the outputs are disabled to the logic-low
state.
Unlike many products containing PLLs, the CSP2510C does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CSP2510C requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for the test purposes by strapping AVDD to ground.
The CSP2510C is specified for operation from 0°C to +85°C. This
device is also available (on special order) in Industrial temperature range
(-40°C to +85°C). See ordering information for details.
3
Y0
4
Y1
5
Y2
8
Y3
9
Y4
CLK
24
FBIN
13
AVDD
23
PLL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
0ºC TO 85ºC TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
1
15
Y5
16
Y6
17
Y7
20
Y8
21
Y9
12
FBOUT
OCTOBER 2000
DSC-5180/2
1 page  
IDTCSP2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0ºC TO 85ºC TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF(1)
VDD = 3.3V ± 0.3V
Parameter (2)
From (Input)
To (Output) Min. Typ. Max.
tPHASE error
tPHASE error – jitter(3)
100MHz < CLK↑ < 133MHz
CLK↑ = 133MHz
FBIN↑
FBIN↑
– 150 150
– 50 50
tSK(o) (4)
Any Y (133MHz)
Any Y
150
Jitter (cycle-cycle)
CLK = 133MHz
Any Y or FBOUT
– 75
75
(peak-to-peak)
Duty cycle reference (5) CLK = 133MHz
Any Y or FBOUT
45
55
tR
Any Y or FBOUT
0.8
2.1
tF
Any Y or FBOUT
0.8
2.7
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C. See PARAMETER MEASUREMENT INFORMATION.
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
3. Phase error does not include jitter.
4. The tSK(O) specification is only valid for equal loading of all outputs.
5. See TYPICAL CHARACTERISTICS.
Unit
ps
ps
ps
ps
%
ns
ns
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDTCSP2510C.PDF ] | |
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