UPSD3214AV-24U1T Datasheet PDF - STMicroelectronics
Part Number | UPSD3214AV-24U1T | |
Description | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM | |
Manufacturers | STMicroelectronics | |
Logo | ||
There is a preview and UPSD3214AV-24U1T download ( pdf file ) link at the bottom of this page. Total 70 Pages |
Preview 1 page No Preview Available ! µPSD323X
Flash Programmable System Devices
with 8032 Microcontroller Core and 64Kbit SRAM
FEATURES SUMMARY
s The µPSD323X Devices combine a Flash PSD
architecture with an 8032 microcontroller core.
The µPSD323X Devices of Flash PSDs feature
dual banks of Flash memory, SRAM, general
purpose I/O and programmable logic, supervi-
sory functions and access via USB, I2C, ADC,
DDC and PWM channels, and an on-board
8032 microcontroller core, with two UARTs,
three 16-bit Timer/Counters and two External
Interrupts. As with other Flash PSD families, the
µPSD323X Devices are also in-system pro-
grammable (ISP) via a JTAG ISP interface.
s Large 8KByte SRAM with battery back-up
option
s Dual bank Flash memories
– 128KByte or 256KByte main Flash memory
– 32KByte secondary Flash memory
s Content Security
– Block access to Flash memory
s Programmable Decode PLD for flexible address
mapping of all memories within 8032 space.
s High-speed clock standard 8032 core (12-cycle)
s USB Interface (some devices only)
s I2C interface for peripheral connections
s 5 Pulse Width Modulator (PWM) channels
s Analog-to-Digital Converter (ADC)
s Standalone Display Data Channel (DDC)
s Six I/O ports with up to 50 I/O pins
s 3000 gate PLD with 16 macrocells
s Supervisor functions with Watchdog Timer
s In-System Programming (ISP) via JTAG
s Zero-Power Technology
s Single Supply Voltage
– 4.5 to 5.5V
– 3.0 to 3.6V
Figure 1. 52-lead, Thin, Quad, Flat Package
TQFP52 (T)
Figure 2. 80-lead, Thin, Quad, Flat Package
TQFP80 (U)
November 2002
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µ PSD323X
STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Serial Port Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Serial Port Control Register (SCON) (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Description of the SCON Bits (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Timer 1-Generated Commonly Used Baud Rates (Table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Serial Port Mode 0, Block Diagram (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Serial Port Mode 0, Waveforms (Figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Serial Port Mode 1, Block Diagram (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Serial Port Mode 1, Waveforms (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Serial Port Mode 2, Block Diagram (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Serial Port Mode 2, Waveforms (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Serial Port Mode 3, Block Diagram (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Serial Port Mode 3, Waveforms (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ADC Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
A/D Block Diagram (Figure 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ADC SFR Memory Map (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Description of the ACON Bits (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC Clock Input (Table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PULSE WIDTH MODULATION (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4-channel PWM unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Four-Channel 8-bit PWM Block Diagram (Figure 36.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PWM SFR Memory Map (Table 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Programmable Period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Programmable PWM 4 Channel Block Diagram (Figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PWM 4 With Programmable Pulse Width and Frequency (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . 76
I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Block Diagram of the I2C Bus Serial I/O (Figure 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Serial Control Register (SxCON: S1CON, S2CON) (Table 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Description of the SxCON Bits (Table 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Selection of the Serial Clock Frequency SCL in Master Mode (Table 52.) . . . . . . . . . . . . . . . . . . . 78
Serial Status Register (SxSTA: S1STA, S2STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Shift Register (SxDAT: S1DAT, S2DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Serial Status Register (SxSTA) (Table 53.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Description of the SxSTA Bits (Table 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Shift Register (SxDAT: S1DAT, S2DAT) (Table 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Address Register (SxADR: S1ADR, S2ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Address Register (SxADR) (Table 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP) (Table 57.) . . . . . . . . . . . . . . . . 80
System Cock of 40MHz (Table 58.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
System Clock Setup Examples (Table 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Programmer’s Guide for I2C and DDC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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