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What is X25642VI-2.7?

This electronic component, produced by the manufacturer "Xicor", performs the same function as "Advanced SPI Serial E 2 PROM with Block Lock TM Protection".


X25642VI-2.7 Datasheet PDF - Xicor

Part Number X25642VI-2.7
Description Advanced SPI Serial E 2 PROM with Block Lock TM Protection
Manufacturers Xicor 
Logo Xicor Logo 


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APPLICATION NOTE
A V A I LABLE
AN19 • AN38 • AN41 • AN61
64K
X25642
8K x 8 Bit
Advanced SPI Serial E2PROM with Block LockTM Protection
FEATURES
2MHz Clock Rate
Low Power CMOS
—<1µA Standby Current
—<5mA Active Current
2.7V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
8K X 8 Bits
—32 Byte Page Mode
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
Packages
—8-Lead PDIP
—8-Lead SOIC
—14-Lead SOIC
—20-Lead TSSOP
DESCRIPTION
The X25642 is a CMOS 65,536-bit serial E2PROM,
internally organized as 8K x 8. The X25642 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25642 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25642 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25642 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25642 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SO
SI
SCK
CS
HOLD
STATUS
REGISTER
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
64
64
128
8K BYTE
ARRAY
64 X 256
64 X 256
128 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct Writeand Block LockProtection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3132-1.0 1/17/97 T5/C0/D1 SH
1
32 8
Y DECODE
DATA REGISTER
3132 ILL F01.1
Characteristics subject to change without notice

line_dark_gray
X25642VI-2.7 equivalent
X25642
Operational Notes
The X25642 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent in-
advertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come HIGH at the proper clock count in or-
der to start a write cycle.
Figure 1. Read E2PROM Array Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
16 BIT ADDRESS
SI
15 14 13
3210
HIGH IMPEDANCE
SO
DATA OUT
76543210
MSB
3132 ILL F03.1
Figure 2. Read Status Register Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION
SI
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
5432
10
3132 ILL F04
5


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for X25642VI-2.7 electronic component.


Information Total 16 Pages
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Featured Datasheets

Part NumberDescriptionMFRS
X25642VI-2.7The function is Advanced SPI Serial E 2 PROM with Block Lock TM Protection. XicorXicor

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