|
|
PDF XC95144XL Data sheet ( Hoja de datos )
| Número de pieza | XC95144XL | |
| Descripción | High Performance CPLD | |
| Fabricantes | Xilinx | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XC95144XL (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
0
R XC95144XL High Performance
CPLD
DS056 (v2.0) April 3, 2007
00
Features
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 144 macrocells with 3,200 usable gates
• Available in small footprint packages
- 100-pin TQFP (81 user I/O pins)
- 144-pin TQFP (117 user I/O pins)
- 144-CSP (117 user I/O pins)
- Pb-free available for all packages
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC95144 device in the
100-pin TQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC95144XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
Product Specification
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See Figure 2 for overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
© 1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS056 (v2.0) April 3, 2007
Product Specification
www.xilinx.com
1
1 page  
R XC95144XL High Performance CPLD
Symbol
IIH
Parameter
I/O high-Z leakage current
CIN I/O capacitance
ICC Operating supply current
(low power mode, active)
Test Conditions
VCC = Max; VCCIO = Max;
VIN = GND or 3.6V
VCC Min < VIN < 5.5V
VIN = GND; f = 1.0 MHz
VIN = GND, No load; f = 1.0 MHz
Min Max Units
- ±10 μA
- ±50
- 10
45 (Typical)
μA
pF
mA
AC Characteristics
Symbol
TPD
TSU
TH
TCO
fSYSTEM
TPSU
TPH
TPCO
TOE
TOD
TPOE
TPOD
TAO
TPAO
TWLH
TAPRPW
TPLH
Parameter
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
P-term S/R to output valid
GCK pulse width (High or Low)
Asynchronous preset/reset pulse width
(High or Low)
P-term clock pulse width (High or Low)
XC95144XL-5
Min Max
- 5.0
3.7 -
0-
- 3.5
- 178.6
1.7 -
2.0 -
- 5.5
- 4.0
- 4.0
- 7.0
- 7.0
- 10.0
- 10.5
2.8 -
5.0 -
XC95144XL-7
Min Max
- 7.5
4.8 -
0-
- 4.5
- 125.0
1.6 -
3.2 -
- 7.7
- 5.0
- 5.0
- 9.5
- 9.5
- 12.0
- 12.6
4.0 -
6.5 -
XC95144XL-10
Min Max
- 10.0
6.5 -
0-
- 5.8
- 100.0
2.1 -
4.4 -
- 10.2
- 7.0
- 7.0
- 11.0
- 11.0
- 14.5
- 15.3
4.5 -
7.0 -
Units
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.0 - 6.5 - 7.0 - ns
Device Output
VTEST
R1
R2
Output Type VCCIO
3.3V
VTEST
3.3V
2.5V
2.5V
CL
Figure 3: AC Load Circuit
R1
320 Ω
250 Ω
R2
360 Ω
660 Ω
CL
35 pF
35 pF
DS058_03_081500
DS056 (v2.0) April 3, 2007
Product Specification
www.xilinx.com
5
5 Page 
R XC95144XL High Performance CPLD
Device Ordering and
Part Marking Number
Speed
(pin-to-pin Pkg.
delay) Symbol
No. of
Pins
Package Type
XC95144XL-10TQG100C 10 ns TQG100 100-pin
Thin Quad Flat Pack (TQFP); Pb-free
XC95144XL-10TQG144C 10 ns TQG144 144-pin
Thin Quad Flat Pack (TQFP); Pb-free
XC95144XL-10CSG144C 10 ns CSG144 144-ball
Chip Scale Package (CSP); Pb-free
XC95144XL-10TQG100I
10 ns TQG100 100-pin
Thin Quad Flat Pack (TQFP); Pb-free
XC95144XL-10TQG144I
10 ns TQG144 144-pin
Thin Quad Flat Pack (TQFP); Pb-free
XC95144XL-10CSG144I
10 ns CSG144 144-ball
Chip Scale Package (CSP); Pb-free
Notes:
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
Operating
Range(1)
C
C
C
I
I
I
Standard Example: XC95144XL -4 TQ
Device
Speed Grade
Package Type
Number of Pins
Temperature Range
144 C
Pb-Free Example: XC95144XL -4 TQ
Device
Speed Grade
Package Type
Pb-Free
Number of Pins
Temperature Range
G 144 C
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing
Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.
Data Sheets, Application Notes, and White Papers.
Packaging
DS056 (v2.0) April 3, 2007
Product Specification
www.xilinx.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet XC95144XL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XC95144XL | High Performance CPLD | Xilinx |
| XC95144XV | High-Performance CPLD | Xilinx |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |