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PDF DOC4106 Data sheet ( Hoja de datos )
| Número de pieza | DOC4106 | |
| Descripción | Single-Chip Microcontroller with MP3 Decoder and Man-Machine Interface | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• MPEG I/II-Layer 3 Hardwired Decoder
– Stand-alone MP3 Decoder
– 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency
– Separated Digital Volume Control on Left and Right Channels (Software Control
Using 31 Steps)
– Bass, Medium, and Treble Control (31 Steps)
– Bass Boost Sound Effect
– Ancillary Data Extraction
– “CRC Error” and “MPEG Frame Synchronization” Indicators
• Programmable Audio Output for Interfacing With Common Audio DAC
– PCM Format Compatible
– I2S Format Compatible
• 8-bit MCU C51 Core Based (FMAX = 20 MHz)
• 2304 Bytes of Internal RAM
• 64K Bytes of Code Memory
– Flash: AT89C51SND1C, ROM: AT83C51SND1C
• 4K Bytes of Boot Flash Memory (AT89C51SND1C)
– ISP: Download from USB or UART to Any External Memory Cards
• USB Rev 1.1 Controller
– “Full Speed” Data Transmission
• Built-in PLL
– MP3 Audio Clocks
– USB Clock
• MultiMedia Card™ Interface Compatibility
• Atmel DataFlash® SPI Interface Compatibility
• IDE/ATAPI Interface
•2 Channels 10-bit ADC, 8 kHz (8-True Bit)
– Battery Voltage Monitoring
– Voice Recording Controlled by Software
• Up to 44 bits of General-purpose I/Os:
– 4-bit Interrupt Keyboard Port for a 4 x n Matrix
– SmartMedia™ Software Interface
• Standard Two 16-bit Timers/Counters
• Hardware Watchdog Timer
• Standard Full Duplex UART with Baud Rate Generator
• Two Wire Interface (TWI) Master and Slave Modes Controller
• SPI Master and Slave Modes Controller
• Power Management
– Power-on Reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
• Operating Conditions:
– 3V, ±10%, 25 mA Typical Operating at 25°C
– Temperature Range: -40°C to +85°C
• Packages
– TQFP80, PLCC84 (Development Board)
– Dice
Single-Chip
Microcontroller
with MP3
Decoder and
Man-Machine
Interface
AT83C51SND1C
AT89C51SND1C
Preliminary
Summary
Description
The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3
decoders with a C51 microcontroller core handling data flow and MP3-player control.
The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Pro-
gramming through an embedded 4K Bytes of Boot Flash Memory.
Rev. 4106F–8051–10/02
1 page  
4106F–8051–10/02
AT8xC51SND1C
Table 1. Ports Signal Description (Continued)
Signal
Name
Type Description
P2.7:0
I/O
Port 2
P2 is an 8-bit bi-directional I/O port with internal pull-ups.
P3.7:0
I/O
Port 3
P3 is an 8-bit bi-directional I/O port with internal pull-ups.
P4.7:0
I/O
Port 4
P4 is an 8-bit bi-directional I/O port with internal pull-ups.
P5.3:0
I/O
Port 5
P5 is a 4-bit bi-directional I/O port with internal pull-ups.
Alternate
Function
A15:8
RXD
TXD
INT0
INT1
T0
T1
WR
RD
MISO
MOSI
SCK
SS
-
Table 2. Clock Signal Description
Signal
Name
Type Description
Input to the on-chip inverting oscillator amplifier
X1
I
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
Output of the on-chip inverting oscillator amplifier
X2 O To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
FILT
I
PLL low pass filter input
FILT receives the RC network of the PLL low pass filter.
Alternate
Function
-
-
-
Table 3. Timer 0 and Timer 1 Signal Description
Signal
Name
Type Description
INT0
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
I External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set,
bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set
by a low level on INT0.
INT1
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by
GATE1 bit in TCON register.
I External Interrupt 1
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set,
bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set
by a low level on INT1.
Alternate
Function
P3.2
P3.3
5
5 Page 
AT8xC51SND1C
Block Diagram
Figure 3. AT8xC51SND1C Block Diagram
INT0 INT1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD T0
33
33 3
T1 SS MISO MOSI SCK SCL SDA
3 44 4 4 1 1
Interrupt
Handler Unit
RAM
2304 Bytes
Flash
ROM
64K Bytes
Flash Boot
4K Bytes
10-bit A-to-D
Converter
or
10-bit ADC
UART
and
BRG
Timers 0/1
Watchdog
SPI/DataFlash
Controller
TWI
Controller
C51 (X2 CORE)
8-BIT INTERNAL BUS
Clock and PLL
Unit
MP3 Decoder
Unit
I2S / PCM
Audio Interface
USB
Controller
MMC
Interface
Keyboard
Interface
I/O
Ports
IDE
Interface
FILT X1 X2 RST
ISP ALE
Note: 1 Alternate function of Port 1
3 Alternate function of Port 3
4 Alternate function of Port 4
DOUT DCLK DSEL SCLK D+ D-
MCLK MDAT MCMD
1
KIN3:0
P0-P5
4106F–8051–10/02
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DOC4106.PDF ] | |
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