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PDF SAA7111A Data sheet ( Hoja de datos )
| Número de pieza | SAA7111A | |
| Descripción | Enhanced Video Input Processor EVIP | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7111A
Enhanced Video Input Processor
(EVIP)
Product specification
Supersedes data of 1997 May 26
File under Integrated Circuits, IC22
1998 May 15
1 page  
Philips Semiconductors
Enhanced Video Input Processor (EVIP)
6 BLOCK DIAGRAM
Product specification
SAA7111A
handbook, full pagewidth
VBI DATA BYPASS
UPSAMPLING FILTER
14
AOUT
AI11
AI12
12
10
AI21
AI22
8
6
n.c.
VSSS
64
13
ANALOG
PROCESSING
AND
ANALOG-TO-
DIGITAL
CONVERSION
AD2 AD1
CON
n.c. 10
ANALOG
PROCESSING
CONTROL
VSSA1-2
VDDA1-2
9,5
11,7
TDI
TCK
TMS
TRST
TDO
3
59
4
58
2
TEST
CONTROL
BLOCK
FOR
BOUNDARY
SCAN TEST
AND
SCAN TEST
BYPASS
CHROMINANCE
CIRCUIT
AND
BRIGHTNESS
C/CVBS CONTRAST
SATURATION
CONTROL
UV
Y
Y
Y/CVBS
LUMINANCE
CIRCUIT
Y
SAA7111A
SYNCHRONIZATION
CIRCUIT
LFCO
57,41,33,25,18 56,40,32,26,19 30 27 17 29 28 60
VDDD1-5
VSSD1-5
VS HS VREF RTS0 RTS1 RTCO
YUV-to-RGB
CONVERSION
AND
OUTPUT
FORMATTER
34 to 39
42 to 51
VPO
(0 : 15)
52 FEI
31 HREF
I2C-BUS
CONTROL
I2C-BUS
INTERFACE
53
GPSW
61 IICSA
62 SDA
63 SCL
CLOCKS
CLOCK
GENERATION
CIRCUIT
POWER-ON
CONTROL
54 XTAL
55
XTALI
21 LLC2
22 CREF
20 LLC
23
RES
15 16 24
VDDA0 VSSA0 CE
MGG061
1998 May 15
Fig.1 Block diagram.
5
5 Page 
Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
The SECAM-processing contains the following blocks:
• Baseband ‘bell’ filters to reconstruct the amplitude and
phase equalized 0 and 90° FM-signals
• Phase demodulator and differentiator
(FM-demodulation)
• De-emphasis filter to compensate the pre-emphasised
input signal, including frequency offset compensation
(DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM-switch signal).
The burst processing block provides the feedback loop of
the chroma PLL and contains;
• Burst gate accumulator
• Colour identification and killer
• Comparison nominal/actual burst amplitude (PAL/NTSC
standards only)
• Loop filter chrominance gain control (PAL/NTSC
standards only)
• Loop filter chrominance PLL (only active for PAL/NTSC
standards)
• PAL/SECAM sequence detection, H/2-switch
generation
• Increment generation for DTO1 with divider to generate
stable subcarrier for non-standard signals.
The chrominance comb filter block eliminates crosstalk
between the chrominance channels in accordance with the
PAL standard requirements. For NTSC colour standards
the chrominance comb filter can be used to eliminate
crosstalk from luminance to chrominance (cross-colour)
for vertical structures. The comb filter can be switched off
if desired. The embedded line delay is also used for
SECAM recombination (cross-over switches).
The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.6).
8.4 Luminance processing
The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f0 = 4.43 or 3.58 MHz centre
frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS and HI8) signals.
The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I2C-bus) in two band-pass filters with selectable transfer
characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.7).
8.5 RGB matrix
Y, Cr and Cb data are converted after interpolation into
RGB data in accordance with CCIR-601
recommendations. The realized matrix equations consider
the digital quantization:
R = Y + 1.371 Cr
G = Y − 0.336 Cb − 0.698 Cr
B = Y + 1.732 Cb.
After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.
8.6 VBI-data bypass
For a 27 MHz VBI-data bypass the offset binary CVBS
signal is upsampled behind the ADCs. Upsampling of the
CVBS signal from 13.5 to 27 MHz is possible, because the
ADCs deliver high performance at 13.5 MHz sample clock.
Suppressing of the back folded CVBS frequency
components after upsampling is achieved by an
interpolation filter (see Fig.42).
The TUF block on the digital top level performs the
upsampling and interpolation for the bypassed CVBS
signal (see Fig.6).
For bypass details see Figs 8 to 10.
8.7 VPO-bus (digital outputs)
The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.
1998 May 15
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA7111A.PDF ] | |
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