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PDF ISL6219 Data sheet ( Hoja de datos )
| Número de pieza | ISL6219 | |
| Descripción | Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
June 2002
ISL6219
FN9080.1
Microprocessor CORE Voltage Regulator
Precision Multi-Phase BUCK PWM
Controller for Mobile Applications
The ISL6219 provides core-voltage regulation by driving up
to three interleaved synchronous-rectified buck-converter
channels in parallel. Intersil multi-phase controllers together
with ISL6207 gate drivers form the basis for the most reliable
power-supply solutions available to power the latest
industry-leading microprocessors. Multi-phase buck-
converter architecture uses interleaved timing to multiply
ripple frequency and reduce input and output ripple currents.
Lower ripple results in lower total component cost, reduced
dissipation, and smaller implementation area. Pre-
configured for 3-phase operation, the ISL6219 also offers 2-
phase operation. Simply connect the unused PWM pin to
+5V. The channel switching frequency is adjustable in the
range of 100kHz to 1.5MHz giving the designer the ultimate
flexibility in managing the balance between high-speed
response and good thermal management.
New features on the ISL6219 include Dynamic-VID™
technology allowing seamless on-the-fly VID changes with
no need for any additional external components. When the
ISL6219 receives a new VID code, it incrementally steps the
output voltage to the new level. Dynamic VID™ changes are
fast and reliable with no output voltage overshoot or
undershoot.
Like other Intersil multiphase controllers, the ISL6219 uses
cost and space-saving rDS(ON) sensing for channel current
balance and dynamic voltage positioning. Channel current
balancing is automatic and accurate with the integrated
current-balance control system. Over current protection can
be tailored to any application with no need of additional
parts.
An integrated DAC decodes the 5-bit logic signal present at
VID0-VID4 and provides an accurate reference for precision
voltage regulation. The high-bandwidth error amplifier and
accurate voltage reference all work together to provide
better than 0.8% total system accuracy, and to enable the
fastest transient response available. A window comparator
toggles PGOOD if the output voltage moves out of range
and acts to protect the load in case of over voltage.
Features
• Multi-Phase Power Conversion
• Active Channel Current Balancing
• Lossless current sense scheme
- Uses MOSFET’s RDS(ON)
- Optional current sense method higher precision
• Precision CORE Voltage Regulation
- ±0.8% System Accuracy Over Temperature
• Microprocessor Voltage Identification Input
- Dynamic VID technology
- 5-Bit VID Input
- 1.100V to 1.850V in 25mV Steps
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Over Voltage, Under Voltage and Overcurrent Protection
• Power-Good Output
• 2 or 3 Phase Operation
• User selectable Switching Frequency of 100K - 1.5MHz
- 200KHz - 4.5MHz Effective Ripple Frequency
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. NO.
ISL6219CA
-10 to 85 28-Ld SSOP M28.15
Pinout
ISL6219 (28 LEAD SSOP)
TOP VIEW
VID 0 1
VID 1 2
VID 2 3
VID 3 4
VID 4 5
NC 6
FSET/EN 7
NC 8
FB 9
COMP 10
NC 11
NC 12
NC 13
GND 14
28 VCC
27 NC
26 NC
25 PGOOD
24 NC
23 ISEN1
22 PWM1
21 PWM2
20 ISEN2
19 ISEN3
18 PWM3
17 NC
16 VSEN
15 NC
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Dynamic VID is a trademark of Intersil Americas Inc.
1 page  
ISL6219
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Recommended Operating Conditions
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . -10oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief TB379 for details.)
Electrical Specifications
Parameter
Operating Conditions: VCC = 5V, TA = -10oC to 85oC, Unless Otherwise Specified
Test Conditions
Min Typ Max Units
INPUT SUPPLY POWER
Input Supply Current
RT = 100kΩ, EN = 5V
- 9.3 15 mA
RT = 100kΩ, EN = 0V
4.5 8.8 14
mA
Power-On Reset Threshold
VCC Rising
4.25 4.38 4.5
V
VCC Falling
3.75 3.88 4.0
V
SYSTEM ACCURACY
System Accuracy
-0.8 - 0.8 %VID
VID Pull Up
- 2.5 -
V
VID Input Low Level
- - 0.8 V
VID Input High Level (Note 3)
2.0 -
-
V
OSCILLATOR
Accuracy
-20 -
20
%
Frequency
RT = 100kΩ (±1%)
224 280 336
kHz
Adjustment Range
Guaranteed by design
100 1500 kHz
Disable Voltage
- 1.23 1.1
V
Sawtooth Amplitude
- 1.54 -
V
Duty-Cycle Range Functional
0 - 75 %
ERROR AMPLIFIER
Open-Loop Gain
Guaranteed by design
- 72 -
dB
Open-Loop Bandwidth
Guaranteed by design
- 18 - MHz
Slew Rate
CL=100pF, RL = 10kΩ to ground
- 5.3 -
V/µs
Maximum Output Voltage
RL = 10kΩ to ground
3.6 4.1
-
V
Minimum Output Voltage
RL = 10kΩ to ground
- 0.23 0.5
V
ISEN
Full Scale Input Current
- 50 -
µA
Over-Current Trip Level
- 75 -
µA
POWER GOOD MONITOR
PGOOD Low Output Voltage
PROTECTION and MONITOR
IPGOOD = 4mA
- 0.18 0.4
V
5
5 Page 
ISL6219
The 11111 VID code is reserved as a signal to the controller
that no load is present. The controller will enter shut-down
mode after receiving this code and will start up upon
receiving any other code.
To enable the controller, VCC must be greater than the POR
threshold; the base of PNP transistor must be greater than
1.23V; and VID cannot be equal to 11111. Once these
conditions are true, the controller immediately initiates a soft
start sequence.
SOFT-START
After the POR function is completed with VCC reaching
4.38V, the soft-start sequence is initiated. Soft-Start, by its
slow rise in CORE voltage from zero, avoids an over-current
condition by slowly charging the output capacitors. This
voltage rise is initiated by an internal DAC that slowly raises
the reference voltage to the error amplifier input. The voltage
rise is controlled by the oscillator frequency and the DAC
within the controller, therefore, the output voltage is
effectively regulated as it rises to the final programmed
CORE voltage value.
For the first 32 PWM switching cycles, the DAC output
remains inhibited and the PWM outputs remain in a high-
impedance state. From the 33rd cycle and for another,
approximately 150 cycles the PWM output remains low,
clamping the lower output MOSFETs to ground. The time
variability is due to the error amplifier, sawtooth generator and
comparators moving into their active regions. After this short
interval, the PWM outputs are enabled and increment the
PWM pulse width from zero duty cycle to operational pulse
width, thus allowing the output voltage to slowly reach the
CORE voltage. The CORE voltage will reach its programmed
value before the 2048 cycles, but the PGOOD output will not
be initiated until the 2048th PWM switching cycle.
The soft-start time, tSS, is determined by an 11-bit counter
that increments with every pulse of the phase clock. For
example, a converter switching at 250kHz has a soft-start
time of
TSS
=
2----0---4----8-
fSW
=
8.2 m s
(EQ. 5)
Figure 9 shows the waveforms when the regulator is
operating at 200kHz. Note that the soft-start duration is a
function of the Channel Frequency as explained previously.
Also note the pulses on the COMP terminal. These pulses
are the current correction signal feeding into the comparator
input (see the Block Diagram).
DYNAMIC VID
The ISL6219 is capable of executing on-the-fly output-
voltage changes. At the beginning of the phase-1 switching
cycle (defined in the section entitled PWM Operation), the
ISL6219 checks for a change in the VID code. The VID code
is the bit pattern present at pins VID4-VID0 as outlined in
Voltage Regulation. If the new code remains stable for
another full cycle, the ISL6219 begins incrementing the
reference by making 25mV change every two switching
cycles until it reaches the new VID code.
Since the ISL6219 recognizes VID-code changes only at the
beginnings of switching cycles, up to one full cycle may pass
before a VID change registers. This is followed by a one-
cycle wait before the output voltage begins to change. Thus,
the total time required for a VID change, tDV, is dependent
on the switching frequency (fS), the size of the change
(∆VID), and the time before the next switching cycle begins.
The one-cycle uncertainty in Equation 6 is due to the
possibility that the VID code change may occur up to one full
cycle before being recognized. The time required for a
converter running with fS = 500kHz to make a 1.5V to 1.7V
reference-voltage change is between 30µs and 32µs as
calculated using Equation 6. This example is also illustrated
in Figure 10
DELAY TIME
V COMP
PGOOD
VCORE
5V
VCC
VIN = 12V
FIGURE 9. START-UP OF 3 PHASE SYSTEM OPERATING AT
200kHz
.
.
--1--
fS
-2---∆----V----I--D--
0.025
–
1
<
tDV
≤
--1--
fS
-2---∆----V----I--D--
0.025
(EQ. 6)
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ISL6219.PDF ] | |
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