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PDF IP1001 Data sheet ( Hoja de datos )
| Número de pieza | IP1001 | |
| Descripción | Full Function Synchronous Buck Power Block | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IP1001 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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PD - 94336c
iP1001
Full Function Synchronous Buck Power Block
Integrated Power Semiconductors, Control IC & Passives
Features
• 3.3V to 12V input voltage1
• 20A maximum load capability, with no derating up to TPCB = 90°C
• 5 bit DAC settable, 0.925V to 2V output voltage range 2
• Configurable down to 3.3Vin & up to 3.3Vout with simple external circuit 3
• 200kHz or 300kHz nominal switching frequency
• Optimized for very low power losses
• Over & undervoltage protection
• Adjustable lossless current limit
• Internal features minimize layout sensitivity *
• Very small outline 14mm x 14mm x 3mm
iP1001 Power Block
Description
The iP1001 is a fully optimized solution for high current synchronous buck applications requiring up to 20A.
The iP1001 is optimized for single-phase applications, and includes a full function fast transient response
PWM control, with an optimized power semiconductor chip-set and associated passives, achieving benchmark
power density. Very few external components are required, including output inductor, input & output capacitors.
Further range of operation to 3.3Vin can be achieved with the addition of a simple external boost circuit, and
operation up to 3.3Vout can be achieved with a simple external voltage divider.
iPOWIR technology offers designers an innovative board space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers
benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout,
heat transfer and component selection.
iP1001 Internal Block Diagram
5 Bit
DAC
D0
D1
D2
D3
D4
ENABLE
PGOOD
IL IM
FREQ
VDD
PWM
& Driver
VIN
VSW
SGND GNDS VFS VF PGND
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be
applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The
iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable
and reliable long term operation. No additional bypassing is required on the Vdd pin. See layout guidelines in datasheet for more detailed information.
www.irf.com
05/20/03
1
1 page  
iP1001
1.36
1.30
1.24
1.18
VIN = 12V
IOUT = 20A
fsw set to 300kHz
TBLK = 125°C
Typical Performance Curves
-13 1.00
-11
0.97
VOUT = 1.3V
-9
-6
0.94
IOUT = 20A
fsw set to 300kHz
TBLK = 125°C
0
1
2
1.12 -4 0.91
3
1.06 -2 0.89
1.00
0
0.94 2 0.86
4
5
0.88
4
0.9 1.3 1.7 2.1 2.5 2.9 3.3
Output Voltage (V)
Fig 3. Normalized Power Loss vs VOUT
0.83 6
3 4 5 6 7 8 9 10 11 12
Input Voltage (V)
Fig 4. Normalized Power Loss vs VIN
25
20
VIN = 5V to 12V
200kHz/300kHz
15
VIN = 3.3V,
200kHz
10
5
0
0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
Output Voltage (V)
Fig 5. Recommended Operating Area
For 200kHz frequency setting there will be a
10% power loss reduction and a positive PCB
temperature adjustment of 3°C.
www.irf.com
5
5 Page 
DESIGN PROCEDURE
Inductor Selection
The inductor is selected according to the following
expression.
L = VOUT x (1-D) / (fsw x ∆IL)
where,
D=V /V
OUT IN
VfsOwUTisisththeesowuittpchuitnvgolftraegqeueinncVyolitns,kHz,
∆IL is the output inductor ripple current.
The inductor value should be selected from 0.8µH
to 2.0µH range.
Output Capacitor Selection
Use tantalum or POSCAP type capacitors for iP1001.
Selection of the output capacitors depends on
several factors.
• Low effective ESR for ripple and load transient
requirements.
• Stability.
To support the load transients and to stay within a
specified voltage dip ∆V due to the transients, ESR
selection should satisfy the following equation:
RESR ≤ ∆V/∆I
where, ∆I is the transient load step
If output voltage ripple is required to be maintained
at specified levels then, the following expression
should be used to select the output capacitors.
RESR ≤ Vp-p / ∆IL
where, Vp-p is the peak to peak output voltage ripple.
The value of the output capacitor ESR zero frequency
also determines stability. The value of the ESR zero
frequency is calculated by the expression:
RESR = 1 / (2π x fESR x COUT)
iP1001
A 470µF POSCAP capacitor has a maximum 35mΩ
of ESR which provides 9.7kHz zero frequency.
The ESR zero frequency must be set below 12kHz.
This value is calculated assuming the capacitor
datasheet maximum ESR value.
Example:
To determine the amount of capacitance
to meet a 30mVp-p output ripple, with 4A
inductor current ripple requirement.
The calculated ESR will be = 30mV/4A =
7.5mΩ. This will require 5 x 470uF POSCAP
capacitors. The total ESR will result in a
9.7kHz zero frequency.
For stable operation:
• Set the resonant frequency fo of the output
inductor and capacitor between 2kHz and 4kHz.
The resonant frequency is calculated using the
following expression:
fo = 1/ (2π x (√LC))
• Select the output inductor value between 0.8µH
to 2.0µH and the output capacitance between
1880µF (4x 470µF) and 5600µF (12x470µF)
• Set the minimum output ripple voltage to be
greater than 0.5% of the output voltage. Select the
capacitor by ESR and by voltage rating rather than
capacitance.
External Input Capacitor Selection
The switching currents impose RMS current
requirements on the input capacitors. The following
expression allows the selection of the input
capacitors, based on the input RMS current:
IRMS = ILOAD x ( √D x (1-D))
where, D = VOUT/VIN
www.irf.com
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet IP1001.PDF ] | |
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