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PDF 73K224L-IGT Data sheet ( Hoja de datos )
| Número de pieza | 73K224L-IGT | |
| Descripción | V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem | |
| Fabricantes | ETC | |
| Logotipo |  |
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73K224L
V.22bis/V.22/V.21/ Bell 212A/Bell 103
Single-Chip Modem
DESCRIPTION
The 73K224L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 bit/s full-duplex operation over dial-up lines. The
73K224L offers excellent performance and a high
level of functional integration in a single 28-pin DIP
and 44-pin TQFP package. This device supports
V.22bis, V.22, V.21, Bell 212A and Bell 103 modes of
operation, allowing both synchronous and
asynchronous communication. The 73K224L is
designed to appear to the systems designer as a
microprocessor peripheral, and will easily interface
with popular single-chip microprocessors (80C51
typical) for control of modem functions through its 8-
bit multiplexed address/data bus or via an optional
serial control bus. An ALE control line simplifies
address demultiplexing. Data communications
normally occur through a separate serial port. The
73K224L is pin and software compatible with the
73K212L and 73K222L single-chip modem ICs,
allowing system upgrades with a single component
change.
The 73K224L operates from a single +5V supply for
low power consumption.
The 73K224L is ideal for use in either free-standing or
integral system modem products where full-duplex
(continued)
BLOCK DIAGRAM
April 2000
FEATURES
• One-chip multi-mode V.22bis/V.22/V.21 and Bell
212A/103 compatible modem data pump
• FSK (300 bit/s), DPSK (600, 1200 bit/s), or QAM
(2400 bit/s) encoding
• Pin and software compatible with other TDK
Semiconductor Corporation K-Series 1-chip
modems
• Interfaces directly with standard microcontrollers
(80C51 typical)
• Parallel microcontroller bus for modem control and
status monitoring functions
• Selectable
asynch/synch
with
internal
buffer/debuffer and scrambler/descrambler
functions
• All synchronous and asynchronous operating
modes (internal, external, slave)
• Adaptive equalization for optimum performance
over all lines
• Programmable transmit attenuation (16 dB, 1 dB
steps), selectable receive boost (+18 dB)
• Call progress, carrier, answer tone, unscrambled
mark, S1, and signal quality monitors
• DTMF, answer and guard tone generators
• Test modes available: ALB, DL, RDL, Mark, Space,
Alternating bit, S1 pattern
• CMOS technology for low power consumption
(typically 100 mW @ 5V) with power-down mode
(15 mW @ 5V)
• TTL and CMOS compatible inputs and outputs
1 page  
73K224L
V.22bis/V.22/V.21/Bell 212A/Bell 103
Single-Chip Modem
DTE USER INTERFACE
NAME
EXCLK
RXCLK
RXD
TXCLK
TXD
TYPE DESCRIPTION
I External Clock. This signal is used in synchronous transmission when the
external timing option has been selected. In the external timing mode the rising
edge of EXCLK is used to strobe synchronous transmit data available on the
TXD pin. Also used for serial control interface.
O/
Tristate
Receive Clock. Tri stateable. The falling edge of this clock output is coincident
with the transitions in the serial received data output. The rising edge of RXCLK
can be used to latch QAM or DPSK valid output data. RXCLK will be active as
long as a carrier is present.
O/ Received Digital Data Output. Serial receive data is available on this pin. The
Weak data is always valid on the rising edge of RXCLK when in synchronous mode.
Pull-up RXD will output constant marks if no carrier is detected.
O/
Tristate
Transmit Clock. Tri stateable. This signal is used in synchronous transmission to
latch serial input data on the TXD pin. Data must be provided so that valid data is
available on the rising edge of the TXCLK. The transmit clock is derived from
different sources depending upon the synchronization mode selection. In Internal
Mode the clock is generated internally. In External Mode TXCLK is phase locked
to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin.
TXCLK is always active.
I Transmit Digital Data Input. Serial data for transmission is input on this pin. In
synchronous modes, the data must be valid on the rising edge of the TXCLK
clock. In asynchronous modes (2400/1200/600 bit/s or 300 baud) no clocking is
necessary. DPSK data must be +1%, -2.5% or +2.3%, -2.5 % in extended
overspeed mode.
ANALOG INTERFACE AND OSCILLATOR
RXA
TXA
XTL1
XTL2
I Received modulated analog signal input from the phone line.
O Transmit analog output to the phone line.
I These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel
I/O mode crystal. Two capacitors from these pins to ground are also required for
proper crystal operation. Consult crystal manufacturer for proper values. XTL2
can also be driven from an external clock.
5
5 Page 
73K224L
V.22bis/V.22/V.21/Bell 212A/Bell 103
Single-Chip Modem
DETECT REGISTER (continued)
D7
D6 D5
D4
D3
D2 D1
D0
DR
RECEIVE
S1
RECEIVE UNSCR.
CARR.
ANSWER
CALL
SIGNAL
010
LEVEL
PATTERN DATA
MARK
DETECT
TONE
PROG.
QUALITY
INDICATOR DETECT
DETECT
DETECT
INDICATOR
BIT NO.
D2
D3
D4
D5
D6
D7
NAME
Answer Tone
Received
Carrier Detect
Unscrambled
Mark Detect
Receive Data
S1 Pattern
Detect
Receive Level
Indicator
CONDITION
0
1
0
1
0
1
0
1
0
1
DESCRIPTION
No answer tone detected.
In Call Init mode, indicates detection of 2225 Hz answer
tone in Bell mode (TR bit D0=0) or 2100 Hz if in CCITT
mode (TR bit D0=1). The device must be in originate mode
for detection of answer tone. Both answer tones are
detected in demod mode.
No carrier detected in the receive channel.
Indicated carrier has been detected in the received
channel.
No unscrambled mark.
Indicates detection of unscrambled marks in the received
data. Should be time qualified by software.
Continuously outputs the received data stream. This data is
the same as that output on the RXD pin, but it is not
disabled when RXD is tri-stated.
No S1 pattern being received.
S1 pattern detected. Should be time qualified by software.
S1 pattern is defined as a double di-bit (001100..)
unscrambled 1200 bit/s DPSK signal. Pattern must be
aligned with baud clock to be detected.
Received signal level below threshold, (typical ≈ -25 dBm0); can
use receive gain boost (+18 dB).
Received signal above threshold.
TONE REGISTER
TR
011
BIT NO.
D7 D6
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD
TONE
NAME
D5 D4 D3
TRANSMIT
ANSWER
TONE
TRANSMIT DTMF 3
DTMF
CONDITION DESCRIPTION
D2
DTMF 2
D1
DTMF 1/
EXTENDED
OVER- SPEED
D0
DTMF 0/
ANSWER/
GUARD
D6 D5 D4 D0 D0 interacts with bits D6, D5, and D4 as shown.
D0
DTMF 0/
X X 1 X Transmit DTMF tones.
Answer/ Guard
Tone
X1
0 0 Select Bell mode answer tone. Interacts with DR bit D2 and
TR bit D5.
X 1 0 1 Select CCITT mode answer tone. Interacts with DR bit D2
and TR bit D5.
11
11 Page | ||
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| PDF Descargar | [ Datasheet 73K224L-IGT.PDF ] | |
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