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PDF HYB25L256160AC-8 Data sheet ( Hoja de datos )
| Número de pieza | HYB25L256160AC-8 | |
| Descripción | 256-Mbit Mobile-RAM | |
| Fabricantes | Infineon Technologies AG | |
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Data Sheet, V1.1, April 2003
HYB25L256160AC
256-Mbit Mobile-RAM
2.5V VDD
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Memory Products
Never stop thinking.
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1 page  
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HYB25L256160AC
256-Mbit Mobile-RAM
Overview
interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
The Mobile-RAM is housed in a FBGA “chip-size” package. The Mobile-RAM is available in the commerical (0 °C
to 70 °C) temperature range.
Table 2 Ordering Information
Part Number1)
Function Code
HYB25L256160AC–7.5
PC133–333–522
HYB25L256160AC–8
PC100–222–620
Case Temperature Range
commerical (0 °C to 70 °C)
1) HYB/E: designator for memory components for commercial/extended temperature range
25L: Mobile-RAM at VDD = 2.5 V
256: 256-Mbit density
160: Product variation x16
A: Die revision A
C: Package type FBGA
–7.5/8: speed grade - see Table 1
Package
P-TFBGA-54
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Data Sheet
5 V1.1, 2003-04-16
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5 Page 
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HYB25L256160AC
256-Mbit Mobile-RAM
Functional Description
MR
Mode Register Definition
(BA[1:0] = 00B)
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00
reg. addr
MODE
w
CL BT BL
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Field Bits Type Description
BL [2:0] w
Burst Length
Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1.
Note: All other bit combinations are RESERVED.
000 1
001 2
010 4
011 8
111 full page (sequential burst type only)
BT 3
w Burst Type
See Table 4 for internal address sequence of low order address bits; see Chapter 3.2.2.
0 Sequential
1 Interleaved
CL [6:4] w
CAS Latency
www.DataSheet4U.comNumber of full clocks from read command to first data valid window; see Chapter 3.2.3.
Note: All other bit combinations are RESERVED.
MODE [12:7] w
010 2
011 3
Operating Mode
See Chapter 3.2.4.
Note: All other bit combinations are RESERVED.
000000 Burst Read/Burst Write
000100 Burst Read/Single Write
3.2.1 Burst Length
Read and write accesses to the 256-Mbit Mobile-RAM are burst oriented, with the burst length being
programmable. The burst length determines the maximum number of column locations that can be accessed for
a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by Ai-A1 when the burst length is set to two, by Ai-A2 when the burst
length is set to four and by Ai-A3 when the burst length is set to eight (where Ai is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies always to Read bursts and depending on
A9 in Operating Mode also on Write bursts.
Data Sheet
11 V1.1, 2003-04-16
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