5962-9054304MXA Datasheet PDF - Intersil Corporation
| Part Number | 5962-9054304MXA | |
| Description | CMOS High Performance Programmable DMA Controller | |
| Manufacturers | Intersil Corporation | |
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82C237
March 1997
CMOS High Performance
Programmable DMA Controller
Features
Description
• Fully Compatible with Intersil 82C37A
- 82C237 May be Used in 8MHz and 12.5MHz 82C37A
Sockets
• Optimized for 10MHz and 12.5MHz 80C286 Systems
• Special Mode Permits 16-Bit, Zero Wait State DMA
Transfers
• High Speed Data Transfers:
- Up to 6.25MBytes/sec with 12.5MHz Clock in
Normal Mode
- Up to 12.5MBytes/sec with 12.5MHz Clock in 16-Bit
Mode
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial-
ization Capability
• Cascadable to any Number of Channels
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
The 82C237 is a modified version of the 82C37A. The
82C237 is fully software and pin for pin compatible with the
82C37A but provides an additional mode for 16-bit DMA
transfers, as well as enhanced speed. Each channel may be
individually programmed for 8-bit or 16-bit data transfers.
The 82C237 controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C237 is designed to be used with an external address
latch, such as the 82C82, to demultiplex the most significant
8 bits of address. An additional latch is required to
temporarily store the most significant 8 bits of data if 16-bit
memory-to-memory transfers are desired. The 82C237 can
be used with industry standard microprocessors such as
80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80,
NSC800, 80186 and others. Multimode programmability
allows the user to select from three basic types of DMA
services, and reconfiguration under program control is
possible even with the clock to the controller stopped. Each
channel has a full 64K address and word count range, and
may be programmed to autoinitialize these registers
following DMA termination (end of process).
Ordering Information
PACKAGE
PDIP
PLCC
SBDIP
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
SMD#
CLCC
SMD#
-55oC to +125oC
8MHz
CP82C237
IP82C237
CS82C237
IS82C237
CD82C237
ID82C237
MD82C237/B
5962-9054304MQA
MR82C237/B
5962-9054304MXA
12.5MHz
CP82C237-12
IP82C237-12
CS82C237-12
IS82C237-12
CD82C237-12
ID82C237-12
MD82C237-12/B
5962-9054305MQA
MR82C237-12/B
5962-9054305MXA
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-148
File Number 2965.1
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82C237
Functional Description
The 82C237 is an improved version of the Intersil 82C37A
DMA controller and is fully software and pin for pin compati-
ble with the 82C37A. All operational and pin descriptions of
the 82C37A apply to the 82C237 with additional features
noted in the section titled 82C237 Operation.
The 82C237 direct memory access controller is designed to
improve the data transfer rate in systems which must
transfer data from an I/O device to memory, or move a block
of memory to an I/O device. It will also perform memory-to-
memory block moves, or fill a block of memory with data
from a single location. Operating modes are provided to
handle single byte transfers as well as discontinuous data
streams, which allows the 82C237 to control data movement
with software transparency.
The DMA controller is a state-driven address and control
signal generator, which permits data to be transferred
directly from an I/O device to memory or vice versa without
ever being stored in a temporary register. This can greatly
increase the data transfer rate for sequential operations,
compared with processor move or repeated string
instructions. Memory-to-memory operations require
temporary internal storage of the data byte between
generation of the source and destination addresses, so
memory-to-memory transfers take place at less than half the
rate of I/O operations, but still much faster than with central
processor techniques. The maximum data transfer rates
obtainable with the 82C237 are shown in Figure 1.
The block diagram of the 82C237 is shown on page 2. The
timing and control block, priority block, and internal registers
are the main components. Figure 2 lists the name and size
of the internal registers. The timing and control block derives
internal timing from CLK input, and generates external
control signals. The Priority Encoder block resolves priority
contention between DMA channels requesting service
simultaneously.
82C237
TRANSFER
TYPE
Compressed
Normal I/O
Memory-to-
Memory
8MHz
12.5MHz
8-BIT 16-BIT 8-BIT 16-BIT UNIT
4.00 8.00 6.25 12.5 MByte/sec
2.67 5.34 4.17 8.34 MByte/sec
1.00 2.00 1.56 3.12 MByte/sec
FIGURE 1. DMA TRANSFER RATES
DMA Operation
In a system, the 82C237 address and control outputs and
data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
address byte. While inactive, the controller’s outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the 82C237
drives the busses and generates the control signals to
perform the data transfer. The operation performed by
activating one of the four DMA request inputs has previously
been programmed into the controller via the Command,
Mode, Address, and Word Count registers.
For example, if a block of data is to be transferred from RAM
to an I/O device, the starting address of the data is loaded
into the 82C237 Current and Base Address registers for a
particular channel, and the length of the block is loaded into
the channel’s Word Count register. The corresponding Mode
register is programmed for a memory-to-I/O operation (read
transfer), and various options are selected by the Command
register and the other Mode register bits. The channel’s
mask bit is cleared to enable recognition of a DMA request
(DREQ). The DREQ can either be a hardware signal or a
software command.
Once initiated, the block DMA transfer will proceed as the
controller outputs the data address, simultaneous MEMR
and IOW pulses, and selects an I/O device via the DMA
acknowledge (DACK) outputs. The data byte flows directly
from the RAM to the I/O device. After each byte is
transferred, the address is automatically incremented (or
decremented) and the word count is decremented. The
operation is then repeated for the next byte. The controller
stops transferring data when the Word Count register
underflows, or an external EOP is applied.
NAME
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Register
Command Register
Temporary Register
Mode Registers
Mask Register
Request Register
Data-Width Register (See Note)
NOTE: 82C237 only
SIZE
16-Bits
16-Bits
16-Bits
16-Bits
16-Bits
16-Bits
8-Bits
8-Bits
8-Bits
6-Bits
4-Bits
4-Bits
4-Bits
NUMBER
4
4
4
4
1
1
1
1
1
4
1
1
1
FIGURE 2. 82C237 INTERNAL REGISTERS
To further understand 82C237 operation, the states
generated by each CLK cycle must be considered. The DMA
controller operates in two major cycles, active and idle. After
being programmed, the controller is normally idle until a
DMA request occurs on an unmasked channel, or a software
request is given. The 82C237 will then request control of the
system busses and enter the active cycle. The active cycle is
composed of several internal states, depending on what
options have been selected and what type of operation has
been requested.
4-152
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