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What is M24C32WDW6T?

This electronic component, produced by the manufacturer "STMicroelectronics", performs the same function as "64/32 Kbit Serial IC Bus EEPROM".


M24C32WDW6T Datasheet PDF - STMicroelectronics

Part Number M24C32WDW6T
Description 64/32 Kbit Serial IC Bus EEPROM
Manufacturers STMicroelectronics 
Logo STMicroelectronics Logo 


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M24C64
M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
Two-Wire I2C Serial Interface
Supports 400kHz Protocol
Single Supply Voltage:
– 4.5 to 5.5V for M24Cxx
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
Write Control Input
BYTE and PAGE WRITE (up to 32 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
Table 1. Product List
Reference
Part Number
M24C64
M24C64
M24C64-W
M24C64-R
M24C32
M24C32
M24C32-W
M24C32-R
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2x3mm² (MLP)
January 2005
1/26

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M24C32WDW6T equivalent
M24C64, M24C32
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to VCC. (Figure 4. indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
rial Data (SDA) to VCC. (Figure 4. indicates how
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7-
bit Device Select Code. These inputs must be tied
to VCC or VSS, to establish the Device Select
Code.
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC) is driven High. When uncon-
nected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
20
16
12
8
4
0
10
fc = 100kHz
fc = 400kHz
100
CBUS (pF)
SDA
MASTER
SCL
RL
RL
CBUS
1000
CBUS
AI01665
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Featured Datasheets

Part NumberDescriptionMFRS
M24C32WDW6TThe function is 64/32 Kbit Serial IC Bus EEPROM. STMicroelectronicsSTMicroelectronics

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