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PDF M28010 Data sheet ( Hoja de datos )
| Número de pieza | M28010 | |
| Descripción | 1 Mbit 128K x 8 Parallel EEPROM With Software Data Protection | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M28010
1 Mbit (128K x 8) Parallel EEPROM
With Software Data Protection
PRELIMINARY DATA
s Fast Access Time: 100 ns
s Single Supply Voltage:
– 4.5 V to 5.5 V for M28010
– 2.7 V to 3.6 V for M28010-W
– 1.8 V to 2.4 V for M28010-R
s Low Power Consumption
s Fast BYTE and PAGE WRITE (up to 128 Bytes)
s Enhanced Write Detection and Monitoring:
– Data Polling
– Toggle Bit
– Page Load Timer Status
s JEDEC Approved Bytewide Pin-Out
s Software Data Protection
s Hardware Data Protection
s Software Chip Erase
s 100000 Erase/Write Cycles (minimum)
s Data Retention (minimum): 10 Years
DESCRIPTION
The M28010 devices consist of 128Kx8 bits of low
power, parallel EEPROM, fabricated with
STMicroelectronics’ proprietary double polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and require a
single voltage supply (5V, 3V or 2V, depending on
the option chosen).
Table 1. Signal Names
A0-A16
Address Input
DQ0-DQ7
Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
VCC
Supply Voltage
VSS Ground
32
1
PDIP32 (BA)
PLCC32 (KA)
TSOP32 (NA)
8 x 20 mm
Figure 1. Logic Diagram
VCC
17
A0-A16
8
DQ0-DQ7
W M28010
E
G
VSS
AI02221
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/23
1 page  
M28010
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 12 and Figure 13). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first).
After a delay, tWLQ5H, that cannot be shorter than
the value specified in Table 9A to Table 9C, the
internal write cycle starts. It continues, under
internal timing control, until the write operation is
complete. The commencement of this period can
be detected by reading the Page Load Timer
Status on DQ5. The end of the internal write cycle
Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write)
SDP is Disabled and Application
needs to Enable it, and Write Data
SDP is Disabled and
Application needs to Enable it
Page Write
Timing
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
Page Write
Timing
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Write data
in any addresses
within one page
Write
is enabled
SDP is set
Write AAh in
Address 5555h
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
Page Write
Timing
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Write data
in any addresses
within one page
Write
is enabled
DATA has been written
and SDP is Enabled
Time Out (tWLQ5H)
Wait for write completion (tQ5HQ5X)
DATA has been written
and SDP is Enabled
AI02227B
5/23
5 Page 
M28010
Table 8B. Read Mode AC Characteristics for M28010-W (3V range)
(TA = –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol Alt.
Parameter
Test
Condi t
ion
–10
Min Max
M28010-W
–12
Min Max
tAVQV tACC Address Valid to Output Valid
E = VIL,
G = VIL
100
120
tELQV tCE Chip Enable Low to Output Valid G = VIL
100
120
tGLQV tOE Output Enable Low to Output Valid E = VIL
70
80
tEHQZ1 tDF Chip Enable High to Output Hi-Z G = VIL 0 50 0 60
tGHQZ1 tDF Output Enable High to Output Hi-Z E = VIL 0 50 0 60
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
0
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
0
–15 Unit
Min Max
150 ns
150 ns
100 ns
0 70 ns
0 70 ns
0 ns
Table 8C. Read Mode AC Characteristics for M28010-R (2V range)
(TA = –40 to 85 °C; VCC = 1.8 to 2.4 V)
Symbol Alt.
Parameter
Test
Condi t
ion
M28010-R
–20 –25
Min Max Min Max
tAVQV tACC Address Valid to Output Valid
E = VIL,
G = VIL
200
250
tELQV tCE Chip Enable Low to Output Valid G = VIL
200
250
tGLQV tOE Output Enable Low to Output Valid E = VIL
80
90
tEHQZ1 tDF Chip Enable High to Output Hi-Z G = VIL
0
50
0
60
tGHQZ1 tDF Output Enable High to Output Hi-Z E = VIL
0
50
0
60
tAXQX
tOH
Address Transition to Output
Transition
E = VIL,
G = VIL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
0
0
Unit
ns
ns
ns
ns
ns
ns
11/23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet M28010.PDF ] | |
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