PDF 1048C Data sheet ( Hoja de datos )

Número de pieza	1048C
Descripción	In-System Programmable High Density PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 1048C/883 In-System Programmable High Density PLD Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Security Cell Prevents Unauthorized Copying • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 50 MHz Maximum Operating Frequency — tpd = 22 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested at Time of Manufacture • IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 A0 A1 A2 A3 Global Routing Pool (GRP) A4 A5 A6 A7 DQ DQ Logic Array D Q GLB DQ D7 D6 D5 D4 D3 D2 D1 D0 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool C0 C1 C2 C3 C4 C5 C6 C7 CLK Output Routing Pool 0139G1A-isp Description The ispLSI 1048C/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD- 883. This military grade device contains 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, two Global Output Enables (GOE), four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048C/883 features 5-Volt in- system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, and the interconnect to provide truly reconfigurable systems. Compared to the ispLSI 1048, the ispLSI 1048C/883 offers two additional dedicated inputs and two new Global Output Enable pins. The basic unit of logic on the ispLSI 1048C/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 in figure 1. There are a total of 48 GLBs in the ispLSI 1048C/883 devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 1048CMIL_01 1 1 page Specifications ispLSI 1048C/883 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 4 COND. #2 DESCRIPTION1 tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 A 1 Data Propagation Delay, 4PT bypass, ORP bypass A 2 Data Propagation Delay A 3 Clock Frequency with Internal Feedback3 – 4 Clock Frequency with External Feedback ( tsu2 1 + )tco1 – 5 Clock Frequency, Max Toggle ( 1 twh + tw1 ) – 6 GLB Reg. Setup Time before Clock, 4PT bypass A 7 GLB Reg. Clock to Output Delay, ORP bypass – 8 GLB Reg. Hold Time after Clock, 4 PT bypass – 9 GLB Reg. Setup Time before Clock – 10 GLB Reg. Clock to Output Delay – 11 GLB Reg. Hold Time after Clock A 12 Ext. Reset Pin to Output Delay – 13 Ext. Reset Pulse Duration B 14 Input to Output Enable C 15 Input to Output Disable B 16 Global OE Output Enable C 17 Global OE Output Disable – 20 Ext. Sync. Clock Pulse Duration, High – 21 Ext. Sync. Clock Pulse Duration, Low – 22 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) – 23 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit counter using GRP feedback. 4. Reference Switching Test Conditions section. -50 UNITS MIN. MAX. – 22.0 ns – 26.0 ns 50.3 – MHz 34.5 – MHz 58.8 – MHz 13.0 – ns – 14.0 ns 0 – ns 15.0 – ns – 16.0 ns 0 – ns – 20.5 ns 13.5 – ns – 27.5 ns – 27.5 ns – 20.5 ns – 20.5 ns 8.5 – ns 8.5 – ns 3.0 – ns 9.0 – ns Table 2- 0030-48C/50 mil 5 5 Page Specifications ispLSI 1048C/883 Pin Configuration ispLSI 1048C/883 133-Pin CPGA Pinout Diagram 14 13 12 11 10 9 87 I/O59 I/O61 I/O64 I/O66 I/O69 IN7 IN8 IN9 6 5 4 3 2 1 PIN A1 IN10 I/O74 I/O75 I/O77 I/O80 I/O83 A I/O56 GND I/O62 I/O65 I/O68 I/O71 GND GOE1 I/O72 I/O76 I/O78 I/O81 GND I/O85 B I/O53 I/O57 I/O60 I/O63 I/O67 I/O70 GND Vcc I/O73 I/O79 I/O82 I/O84 I/O86 I/O88 C I/O51 I/O54 I/O58 INDEX I/O87 I/O89 I/O90 D I/O50 I/O52 I/O55 IN6 I/O48 I/O49 Y1 Vcc Vcc Y3 Y2 GND ispLSI 1048C/883 Bottom View I/O91 I/O92 I/O93 E I/O94 I/O95 IN11 F Vcc Vcc Y0 G GND ispEN RESET H SCLK/ IN51 I/O47 I/O46 I/O45 I/O44 I/O43 I/O1 I/O0 SDI/ IN01 J I/O7 I/O4 I/O2 K I/O42 I/O41 I/O39 I/O10 I/O6 I/O3 L I/O40 I/O38 I/O36 I/O34 I/O31 I/O25 GND Vcc I/O22 I/O19 I/O15 I/O12 I/O9 I/O5 M I/O37 GOE0 I/O33 I/O30 I/O28 I/O24 GND Vcc I/O23 I/O20 I/O17 I/O14 GND I/O8 N I/O35 I/O32 I/O29 I/O27 I/O26 IN4 SDO/ IN31 IN2 MODE/ IN11 I/O21 I/O18 I/O16 I/O13 I/O11 P 1. Pins have dual function capability. 133 CPGA Pinout.eps 11 11 Page

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