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PDF ATMEGA161L Data sheet ( Hoja de datos )
| Número de pieza | ATMEGA161L | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 8 MIPS Throughput at 8 MHz
– On-chip 2-cycle Multiplier
• Program and Data Memories
– 16K Bytes of Non-volatile In-System Programmable Flash Endurance: 1,000
Write/Erase Cycles
– Optional Boot Code Memory with Independent Lock bits Self-programming of
Program and Data Memories
– 512 Bytes of Non-volatile In-System Programmable EEPROM Endurance: 100,000
Write/Erase Cycles
– 1K Byte of Internal SRAM
– Programming Lock for Software Security
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,
Capture Modes and Dual 8-, 9-, or 10-bit PWM
– Dual Programmable Serial UARTs
– Master/Slave SPI Serial Interface
– Real-time Counter with Separate Oscillator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power-save and Power-down
• Power Comsumption at 4 MHz, 3.0V, 25°C
– Active 3.0 mA
– Idle Mode 1.2 mA
– Power-down Mode < 1 µA
• I/O and Packages
– 35 Programmable I/O Lines
– 40-lead PDIP and 44-lead TQFP
• Operating Voltages
– 2.7V - 5.5V for the ATmega161L
– 4.0V - 5.5V for the ATmega161
• Speed Grades
– 0 - 4 MHz for the ATmega161L
– 0 - 8 MHz for the ATmega161
• Commercial and Industrial Temperature Ranges
8-bit
Microcontroller
with 16K Bytes
of In-System
Programmable
Flash
ATmega161
ATmega161L
Disclaimer
Typical values contained in this data sheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology.
Min and Max values will be available after the device is characterized.
Note: Not recommended in new
designs.
Rev. 1228D–AVR–02/07
1
1 page  
Pin Descriptions
VCC
GND
Port A (PA7..PA0)
Port B (PB7..PB0)
Port C (PC7..PC0)
Port D (PD7..PD0)
Port E (PE2..PE0)
RESET
XTAL1
XTAL2
ATmega161(L)
Supply voltage.
Ground.
Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-
plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,
they will source current if the internal pull-up resistors are activated. The Port A pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port A serves as a Multiplexed Address/Data port when using external memory
interface.
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega161 as listed
on page 92.
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output
buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves as an address high output when using external memory interface.
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega161 as listed
on page 101.
Port E is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port E output
buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega161 as listed
on page 107.
Reset input. A low level on this pin for more than 500 ns will generate a Reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
1228D–AVR–02/07
5
5 Page 
ATmega161(L)
In the different Addressing modes, these address registers have functions as fixed dis-
placement, automatic increment and decrement (see the descriptions for the different
instructions).
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, ALU operations between regis-
ters in the Register File are executed. The ALU operations are divided into three main
categories – arithmetic, logical and bit functions. ATmega161 also provides a powerful
multiplier supporting both signed/unsigned multiplication and fractional format. See the
Instruction Set section for a detailed description.
Self-programmable Flash
Program Memory
The ATmega161 contains 16K bytes of On-chip Self-programmable and In-System Pro-
grammable Flash memory for program storage. Since all instructions are 16- or 32-bit
words, the Flash is organized as 8K x 16. The Flash memory has an endurance of at
least 1,000 write/erase cycles. The ATmega161 Program Counter (PC) is 13 bits wide,
thus addressing the 8,192 Program memory locations.
See page 110 for a detailed description of Flash data downloading.
See page 13 for the different Program Memory Addressing modes.
EEPROM Data Memory
The ATmega161 contains 512 bytes of data EEPROM memory. It is organized as a sep-
arate data space in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles per location. The interface between the
EEPROM and the CPU is described on page 60, specifying the EEPROM Address Reg-
isters, the EEPROM Data Register and the EEPROM Control Register.
For the SPI data downloading, see page 125 for a detailed description.
1228D–AVR–02/07
11
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