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PDF ATMEGA128 Data sheet ( Hoja de datos )
| Número de pieza | ATMEGA128 | |
| Descripción | 8-bit Atmel Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High-performance, Low-power Atmel®AVR®8-bit Microcontroller
• Advanced RISC Architecture
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 128Kbytes of In-System Self-programmable Flash program memory
– 4Kbytes EEPROM
– 4Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Up to 64Kbytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
• QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture
Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
• I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V ATmega128L
– 4.5 - 5.5V ATmega128
• Speed Grades
– 0 - 8MHz ATmega128L
– 0 - 16MHz ATmega128
8-bit Atmel
Microcontroller
with 128KBytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Rev. 2467X–AVR–06/11
1 page  
ATmega128
ATmega103
Compatibility Mode
Pin Descriptions
VCC
GND
Port A (PA7..PA0)
Port B (PB7..PB0)
The ATmega128 is 100% pin compatible with ATmega103, and can replace the ATmega103 on
current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128”
describes what the user should be aware of replacing the ATmega103 by an ATmega128.
By programming the M103C fuse, the Atmel®ATmega128 will be compatible with the
ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some
new features in ATmega128 are not available in this compatibility mode, these features are
listed below:
• One USART instead of two, Asynchronous mode only. Only the eight least significant bits of
the Baud Rate Register is available.
• One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters
with three compare registers.
• Two-wire serial interface is not supported.
• Port C is output only.
• Port G serves alternate functions only (not a general I/O port).
• Port F serves as digital input only in addition to analog input to the ADC.
• Boot Loader capabilities is not supported.
• It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
• The External Memory Interface can not release any Address pins for general I/O, neither
configure different wait-states to different External Memory Address sections.
In addition, there are some other minor differences to make it more compatible to ATmega103:
• Only EXTRF and PORF exists in MCUCSR.
• Timed sequence not required for Watchdog Time-out change.
• External Interrupt pins 3 - 0 serve as level interrupt only.
• USART has no FIFO buffer, so data overrun comes earlier.
Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega128.
Digital supply voltage.
Ground.
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega128 as listed on page
72.
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega128 as listed on page
73.
2467X–AVR–06/11
5
5 Page 
ATmega128
General Purpose
Register File
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared in
software with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register file can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register file by the BLD
instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a half carry in some arithmetic operations. Half carry is useful in
BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement over-
flow flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
The Register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the
Register file:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4 on page 12 shows the structure of the 32 general purpose working registers in the
CPU.
2467X–AVR–06/11
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATMEGA128.PDF ] | |
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