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PDF ATF22V10CZ Data sheet ( Hoja de datos )
| Número de pieza | ATF22V10CZ | |
| Descripción | High-performance Electrically Erasable Programmable Logic Device | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Industry-standard Architecture
• 12ns Maximum Pin-to-pin Delay
• Zero Power – 100µA Maximum Standby Power (Input Transition Detection)
• CMOS and TTL Compatible Inputs and Outputs
• Advanced Electrically ErasableTechnology
– Reprogrammable
– 100% Tested
• Latch Feature Holds Inputs to Previous Logic State
• High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200mA Latchup Immunity
• Industrial Temperature Ranges
• Dual-in-line and Surface Mount Standard Pinouts
• PCI Compliant
• Green Package Options (Pb/Halide-free/RoHS Compliant) Available
High-performance
Electrically
Erasable
Programmable
Logic Device
1. Description
The Atmel® ATF22V10CZ/CQZ is a high-performance CMOS (electrically erasable)
programmable logic device (PLD) which utilizes The Atmel proven electrically eras-
able Flash memory technology. Speeds down to 12ns with zero standby power
dissipation are offered. All speed ranges are specified over the full 5V ±10% range for
industrial temperature ranges; 5V ±5% for commercial range 5-volt devices. The
ATF22V10CZ/CQZ provides a low voltage and edge-sensing “zero” power CMOS
PLD solution with “zero” standby power (5µA typical). The ATF22V10CZ/CQZ pro-
vides a “zero” power CMOS PLD solution with 5V operating voltages, powering down
automatically to the zero power-mode through The Atmel patented Input Transition
Detection (ITD) circuitry when the device is idle, offering “zero” (100µA worst case)
standby power. This feature allows the user to manage total system power to meet
specific application requirements and enhance reliability. Pin “keeper” circuits on input
and output pins eliminate static power consumed by pull-up resistors. The “CQZ” com-
bines the low high-frequency ICC of the “Q” design with the “Z” feature.
The ATF22V10CZ/CQZ incorporates a superset of the generic architectures, which
allows direct replacement of the 22V10 family and most 24-pin combinatorial PLDs.
Ten outputs are each allocated 8 to 16 product terms. Three different modes of opera-
tion, configured automatically with software, allow highly complex logic functions to be
realized.
Atmel ATF22V10CZ
Atmel ATF22V10CQZ
ATF22V10CZ is
Not Recommended for New
Design. Replaced by
ATF22V10CQZ.
0778L–PLD–8/10
1 page  
4.4 Input Test Waveforms
4.4.1 Input Test Waveforms and Measurement Levels
Atmel ATF22V10C(Q)Z
4.4.2 Output Test Loads
Note:
Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’
delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification
conditions.
4.5 Pin Capacitance
Table 4-1. Pin Capacitance (f = 1MHz, T = 25C(1)
CIN
CI/O
Note:
Typ Max
Units
Conditions
8 10
pF
VIN = 0V; f = 1.0MHz
8 10
pF
VOUT = 0V; f = 1.0MHz
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
4.6 Power-up Reset
The registers in the Atmel® ATF22V10CZ/CQZ are designed to reset during power-up. At a point delayed slightly
from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic and start below 0.7V
2. The clock must remain stable during TPR
3. After TPR occurs, all input and feedback setup times must be met before driving the clock pin high
4.7 Preload of Register Outputs
The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
0778L–PLD–8/10
5
5 Page 
Atmel ATF22V10C(Q)Z
ATMEL ATF22V10CZ/CQZ INPUT CLAMP
CURRENT VS INPUT VOLTAGE (VCC = 5V, TA = 35°C)
0
-20
-40
-60
-80
-100
-120
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
INPUT VOLTAGE (V)
1.2
1.1
1.0
0.9
0.8
4.5
NORMALIZED TPD vs. VCC
4.8 5.0 5.3
SUPPLY VOLTAGE (V)
1.3
1.2
1.1
1.0
0.9
0.8
4.5
NORMALIZED TCO vs.VCC
4.8 5.0 5.3
SUPPLY VOLTAGE (V)
1.2
1.1
1.0
0.9
0.8
4.5
NORMALIZED TSU VS VCC
4.8 5.0 5.3
SUPPLY VOLTAGE (V)
5.5
5.5
5.5
ATMEL ATF22V10CZ/CQZ INPUT CURRENT
VS INPUT VOLTAGE (VCC = 5V, TA = 25°C)
40
30
20
10
0
-10
-20
-30
0.0 1.0 2.0 3.0 4.0 5.0 6.0
INPUT VOLTAGE (V)
1.1
1.0
0.9
0.8
-40.0
NORMALIZED TPD vs. TEMP
0.0 25.0
TEMPERATURE (C)
75.0
1.1
1.0
0.9
0.8
-40.0
NORMALIZED TCO VS TEMP
0.0 25.0
TEMPERATURE (V)
1.2
1.1
1.0
0.9
0.8
-40.0
NORMALIZED TSU vs. TEMP
0.0 25.0
TEMPERATURE (C)
75.0
75.0
0778L–PLD–8/10
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ATF22V10CZ.PDF ] | |
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