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PDF 39SF020 Data sheet ( Hoja de datos )
| Número de pieza | 39SF020 | |
| Descripción | 2 Megabit (256K x 8) Multi-Purpose Flash | |
| Fabricantes | Silicon Storage Technology Inc | |
| Logotipo |  |
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2 Megabit (256K x 8) Multi-Purpose Flash
SST39SF020
Preliminary Specifications
FEATURES:
• Organized as 256 K X 8
• Single 5.0V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
• Sector Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Time:
– 70 and 90 ns
• Latched Address and Data
• Fast Sector Erase and Byte Program:
– Sector Erase Time: 7 ms (typical)
– Chip Erase Time: 15 ms (typical)
– Byte Program time: 20 µs (typical)
– Chip Rewrite Time: 5 seconds (typical)
• Automatic Write Timing
- Internal Vpp Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• TTL I/O Compatibility
• JEDEC Standard
– EEPROM Pinouts and command set
• Packages Available
– 32-Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST39SF020 is a 256K x 8 CMOS Multi-Purpose
Flash (MPF) manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The split
gate cell design and thick oxide tunneling injector attain
better reliability and manufacturability compared with
alternate approaches. The SST39SF020 device writes
(Program or Erase) with a 5.0V-only power supply. The
SST39SF020 device conforms to JEDEC standard
pinouts for x8 memories.
Featuring high performance byte program, the
SST39SF020 device provides a maximum byte-pro-
gram time of 30 µsec. The entire memory can be erased
and programmed byte by byte typically in 5 seconds,
when using interface features such as Toggle Bit or
Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, the
SST39SF020 device has on-chip hardware and soft-
ware data protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, the
SST39SF020 device is offered with a guaranteed endur-
ance of 10,000 cycles. Data retention is rated at greater
than 100 years.
The SST39SF020 device is suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applica-
tions, the SST39SF020 device significantly improves
performance and reliability, while lowering power
consumption. The SST39SF020 inherently uses less
energy during erase and program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application.
Since for any given voltage range, the SuperFlash tech-
nology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase
or Program operation is less than alternative flash tech-
nologies. The SST39SF020 device also improves flex-
ibility while lowering the cost for program, data, and
configuration storage applications.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of endurance
cycles that have occurred. Therefore the system soft-
ware or hardware does not have to be modified or de-
rated as is necessary with alternative flash technologies,
whose erase and program times increase with accumu-
lated endurance cycles.
To meet high density, surface mount requirements, the
SST39SF020 device is offered in 32-pin TSOP and 32-
pin PLCC packages. A 600 mil, 32-pin PDIP is also
available. See Figures 1 and 2 for pinouts.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write sequences.
A command is written by asserting WE# low while
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© 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc.
326-10 12/98
1 These specifications are subject to change without notice.
1 page  
2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
A17-A0
Address Inputs
DQ7-DQ0 Data Input/output
CE#
OE#
WE#
Vcc
Vss
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Functions
To provide memory addresses. During sector erase A17-A12 address lines
will select the sector.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations.
To provide 5-volt supply (± 10%)
Unconnected pins.
326 PGM T2.1
1
2
3
4
5
TABLE 3: OPERATION MODES SELECTION
Mode
CE# OE#
Read
VIL VIL
Program
Erase
VIL VIH
VIL VIH
Standby
Write Inhibit
Product Identification
Hardware Mode
Software Mode
VIH X
X VIL
XX
VIL VIL
VIL VIL
WE#
VIH
VIL
VIL
A9
AIN
AIN
X
XX
XX
VIH X
VIH VH
VIH AIN
DQ
DOUT
DIN
X
High Z
High Z/DOUT
High Z/DOUT
Address
AIN
AIN
Sector address, XXh for
chip erase
X
X
X
Manufacturer Code (BF)
Device Code (B6)
ID Code
A17 - A1 = VIL, A0 = VIL
A17 - A1 = VIL, A0 = VIH
See Table 4
326 PGM T3.4
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© 1998 Silicon Storage Technology, Inc.
5
326-10 12/98
5 Page 
2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
ADDRESS A17-0
CE#
TAS
OE#
WE#
DQ7-0
5555
TAH
TCP
2AAA
TCPH
5555
ADDR
INTERNAL PROGRAM OPERATION STARTS
TBP
TDH
TDS
TCH
AA
SW0
TCS
55
A0
DATA
SW1
SW2
BYTE
(ADDR/DATA)
326 ILL F05.3
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
1
2
3
4
5
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8
9
ADDRESS A17-0
CE#
OE#
WE#
DQ7
TOEH
TCE
TOE
D D#
10
11
TOES
12
13
D# D
14
326 ILL F06.0
15
FIGURE 6: DATA# POLLING TIMING DIAGRAM
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© 1998 Silicon Storage Technology, Inc.
11
326-10 12/98
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet 39SF020.PDF ] | |
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