37LV36-L Datasheet PDF - Microchip Technology
Part Number | 37LV36-L | |
Description | 36K/ 64K/ and 128K Serial EPROM Family | |
Manufacturers | Microchip Technology | |
Logo | ||
There is a preview and 37LV36-L download ( pdf file ) link at the bottom of this page. Total 12 Pages |
Preview 1 page No Preview Available ! 37LV36/65/128
36K, 64K, and 128K Serial EPROM Family
FEATURES
• Operationally equivalent to Xilinx® XC1700 family
• Wide voltage range 3.0 V to 6.0 V
• Maximum read current 10 mA at 5.0 V
• Standby current 100 µA typical
• Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
• Full Static Operation
• Sequential Read/Program
• Cascadable Output Enable
• 10 MHz Maximum Clock Rate @ 5.0 Vdc
• Programmable Polarity on Hardware Reset
• Programming with industry standard EPROM pro-
grammers
• Electrostatic discharge protection > 4,000 volts
• 8-pin PDIP/SOIC and 20-pin PLCC packages
• Data Retention > 200 years
• Temperature ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V VCC range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
Device Bits Programming Word
37LV36
37LV65
37LV128
36,288
65,536
131,072
1134 x 32
2048 x 32
4096 x 32
Xilinx is a registered trademark of Xilinx Corporation.
PACKAGE TYPES
PDIP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 VPP
6 CEO
5 VSS
SOIC
DATA
CLK
RESET/OE
CE
PLCC
18
27
36
45
DATA VCC
VCC
VPP
CEO
VSS
CLK 4
5
RESET/OE 6
7
CE 8
18
17 VPP
16
15
14 CEO
Vss
BLOCK DIAGRAM
CE
RESET/OE
CEO
ADDRESS EPROM
Counter ARRAY
CLK
OE
DATA
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS21109E-page 1
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37LV36/65/128
FIGURE 11-2: READ CHARACTERISTICS AT END OF ARRAY TIMING
RESET/OE
CE
CLK
DATA
CEO
T CDF
LAST BIT
T OCK
TOCE
TOOE
FIRST BIT
T OCE
TABLE 11-2: READ CHARACTERISTICS AT END OF ARRAY
AC Testing Waveform: VIL = 0.2V; VIH = 3.0V
AC Test Load: 50 pF
VOL = VOL_MAX; VOH = VOH_MIN
Symbol
Parameter
Limits 3.0V ≤ Vcc ≤ Limits 4.5V ≤ Vcc ≤
6.0V
6.0V
Min.
Max.
Min.
Max.
Units
TCDF CLK to Data Float Delay
— 50 — 50
TOCK CLK to CEO Delay
— 65 — 40
TOCE CE to CEO Delay
— 45 — 40
TOOE RESET/OE to CEO Delay
— 45 — 40
Note 1: This parameter is periodically sampled and not 100% tested.
2: Float delays are measured with output pulled through 1kΩ to VLOAD = VCC/2.
ns
ns
ns
ns
Conditions
Notes 1, 2
© 1996 Microchip Technology Inc.
DS21109E-page 5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 37LV36-L electronic component. |
Information | Total 12 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ 37LV36-L.PDF Datasheet ] |
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