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PDF 376 Data sheet ( Hoja de datos )
| Número de pieza | 376 | |
| Descripción | 376TM HIGH PERFORMANCE 32-BIT EMBEDDED PROCESSOR | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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376TM HIGH PERFORMANCE
32-BIT EMBEDDED PROCESSOR
Y Full 32-Bit Internal Architecture
8- 16- 32-Bit Data Types
8 General Purpose 32-Bit Registers
Extensive 32-Bit Instruction Set
Y High Performance 16-Bit Data Bus
16 or 20 MHz CPU Clock
Two-Clock Bus Cycles
16 Mbytes Sec Bus Bandwidth
Y 16 Mbyte Physical Memory Size
Y High Speed Numerics Support with the
80387SX
Y Low System Cost with the 82370
Integrated System Peripheral
Y On-Chip Debugging Support Including
Break Point Registers
Y Complete Intel Development Support
C PL M Assembler
ICETM-376 In-Circuit Emulator
iRMK Real Time Kernel
iSDM Debug Monitor
DOS Based Debug
Y Extensive Third-Party Support
Languages C Pascal FORTRAN
BASIC and ADA
Hosts VMS UNIX MS-DOS and
Others
Real-Time Kernels
Y High Speed CHMOS IV Technology
Y Available in 100 Pin Plastic Quad Flat-
Pack Package and 88-Pin Pin Grid Array
(See Packaging Outlines and Dimensions 231369)
INTRODUCTION
The 376 32-bit embedded processor is designed for high performance embedded systems It provides the
performance benefits of a highly pipelined 32-bit internal architecture with the low system cost associated with
16-bit hardware systems The 80376 processor is based on the 80386 and offers a high degree of compatibil-
ity with the 80386 All 80386 32-bit programs not dependent on paging can be executed on the 80376 and all
80376 programs can be executed on the 80386 All 32-bit 80386 language translators can be used for
software development With proper support software any 80386-based computer can be used to develop and
test 80376 programs In addition any 80386-based PC-AT compatible computer can be used for hardware
prototyping for designs based on the 80376 and its companion product the 82370
80376 Microarchitecture
240182 – 48
Intel iRMK ICE 376 386 Intel386 iSDM Intel1376 are trademarks of Intel Corp
UNIX is a registered trademark of AT T
ADA is a registered trademark of the U S Government Ada Joint Program Office
PC-AT is a registered trademark of IBM Corporation
VMS is a trademark of Digital Equipment Corporation
MS-DOS is a trademark of MicroSoft Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
December 1990
Order Number 240182-004
1 page  
376 EMBEDDED PROCESSOR
The following table lists a brief description of each pin on the 80376 The following definitions are used in
these descriptions
The named signal is active LOW
I Input signal
O Output signal
I O Input and Output signal
No electrical connection
Symbol
CLK2
RESET
D15 – D0
A23 – A1
WR
DC
M IO
LOCK
ADS
NA
READY
BHE BLE
HOLD
Type
I
I
IO
O
O
O
O
O
O
I
I
O
I
Name and Function
CLK2 provides the fundamental timing for the 80376 For additional
information see Clock in Section 4 1
RESET suspends any operation in progress and places the 80376 in a
known reset state See Interrupt Signals in Section 4 1 for additional
information
DATA BUS inputs data during memory I O and interrupt acknowledge
read cycles and outputs data during memory and I O write cycles See
Data Bus in Section 4 1 for additional information
ADDRESS BUS outputs physical memory or port I O addresses See
Address Bus in Section 4 1 for additional information
WRITE READ is a bus cycle definition pin that distinguishes write
cycles from read cycles See Bus Cycle Definition Signals in Section
4 1 for additional information
DATA CONTROL is a bus cycle definition pin that distinguishes data
cycles either memory or I O from control cycles which are interrupt
acknowledge halt and instruction fetching See Bus Cycle Definition
Signals in Section 4 1 for additional information
MEMORY I O is a bus cycle definition pin that distinguishes memory
cycles from input output cycles See Bus Cycle Definition Signals in
Section 4 1 for additional information
BUS LOCK is a bus cycle definition pin that indicates that other
system bus masters are denied access to the system bus while it is
active See Bus Cycle Definition Signals in Section 4 1 for additional
information
ADDRESS STATUS indicates that a valid bus cycle definition and
address (W R D C M IO BHE BLE and A23 – A1) are being driven at
the 80376 pins See Bus Control Signals in Section 4 1 for additional
information
NEXT ADDRESS is used to request address pipelining See Bus
Control Signals in Section 4 1 for additional information
BUS READY terminates the bus cycle See Bus Control Signals in
Section 4 1 for additional information
BYTE ENABLES indicate which data bytes of the data bus take part in
a bus cycle See Address Bus in Section 4 1 for additional
information
BUS HOLD REQUEST input allows another bus master to request
control of the local bus See Bus Arbitration Signals in Section 4 1
for additional information
5
5 Page 
376 EMBEDDED PROCESSOR
240182 – 6
Figure 2 3 Address Translation
SEGMENT REGISTER USAGE
The main data structure used to organize memory is
the segment On the 80376 segments are variable
sized blocks of linear addresses which have certain
attributes associated with them There are two main
types of segments code and data The simplest use
of segments is to have one code and data segment
Each segment is 16 Mbytes in size overlapping each
other This allows code and data to be directly ad-
dressed by the same offset
ister is used The segment register is automatically
chosen according to the rules of Table 2 3 (Segment
Register Selection Rules) In general data refer-
ences use the selector contained in the DS register
stack references use the SS register and instruction
fetches use the CS register The contents of the In-
struction Pointer provide the offset Special segment
override prefixes allow the explicit use of a given
segment register and override the implicit rules list-
ed in Table 2 3 The override prefixes also allow the
use of the ES FS and GS segment registers
In order to provide compact instruction encoding
and increase processor performance instructions
do not need to explicitly specify which segment reg-
There are no restrictions regarding the overlapping
of the base addresses of any segments Thus all 6
segments could have the base address set to zero
Further details of segmentation are discussed in
Section 3 0 Architecture
11
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| PDF Descargar | [ Datasheet 376.PDF ] | |
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