30071-53 Datasheet PDF - National Semiconductor
Part Number | 30071-53 | |
Description | Geode GXm Processor Integrated x86 Solution with MMX Support | |
Manufacturers | National Semiconductor | |
Logo | ||
There is a preview and 30071-53 download ( pdf file ) link at the bottom of this page. Total 30 Pages |
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Geode™ GXLV Processor Series
Low Power Integrated x86 Solutions
General Description
The National Semiconductor® Geode™ GXLV processor
series is a new line of integrated processors specifically
designed to power information appliances for entertain-
ment, education, and business. Serving the needs of con-
sumers and business professionals alike, it is the perfect
solution for information appliance applications such as
thin clients, interactive set top boxes, and personal inter-
net access devices.
The GXLV processor series is divided into three main cat-
egories as defined by the core operating voltage. Avail-
able with core voltages of 2.2V, 2.5V, and 2.9V, it offers
extremely low typical power consumption (1.0W to 2.5W)
leading to longer battery life and enabling small form-fac-
tor, fanless designs. Each core voltage is offered in fre-
quencies that are enabled by specific system clock and
multiplier settings. This allows the user to select the
device(s) that best fit their power and performance
requirements. This flexibility makes the GXLV processor
series ideally suited for applications where power con-
sumption and performance (speed) are equally important.
Typical power consumption is defined as an average,
measured running Microsoft’s Windows at 80% Active Idle
(Suspend-on-Halt) with a display resolution of 800x600x8
bpp at 75 Hz.
Internal Block Diagram
SYSCLK
Clock Module
SYSCLK
multiplied by
A
Core
Clocks
X-Bus
Clocks
16 KB
Unified L1
Cache
(128)
X86 Compatible Core
Integer
TLB Unit
Instruction
Fetch
MMU
Load/Store
INT/NMI
Interrupt
Control
FP_Error
Floating Point
Unit
INTR
IRQ13
SMI#
C-Bus (64)
SUSP#
SUSPA#
Power
Management
Control
Core Suspend
Core Acknowledge
X-Bus Suspend
X-Bus Acknowledge
X-Bus (32)
Arbiter
Write Buffers
X-Bus Controller
Read Buffers
PCI Host
Arbiter Controller
2D Accelerator
VGA
BLT Engine
ROP Unit
X-Bus Clk ÷ B
Display Controller
Compression Buffer
Palette RAM
Timing Generator
3
REQ/GNT
Pairs
PCI Bus
4
SDRAM
Clocks
64-bit SDRAM
RGB
YUV
Video Companion Interface
National Semiconductor is a registered trademark of National Semiconductor Corporation.
Geode and WebPAD are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor® Corporation
www.national.com
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Table of Contents (Continued)
3.5
3.6
3.7
3.8
3.9
3.10
3.11
OFFSET, SEGMENT, AND PAGING MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.5.1 Offset Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.5.2 Segment Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
Real Mode Segment Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Virtual 8086 Mode Segment Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Segment Mechanism in Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Segment Selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.5.3 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.5.3.1 Global and Local Descriptor Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.5.3.2 Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.5.3.3 Task, Gate, Interrupt, and Application and System Descriptors . . . . . . . . . . . . . . 71
3.5.4 Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
INTERRUPTS AND EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.6.2 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.6.3 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.3.1 Interrupt Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.3.2 Interrupt Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.4 Interrupt and Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.6.5 Exceptions in Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.6.6 Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SYSTEM MANAGEMENT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.7.1 SMM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.7.2 SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.7.3 SMM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.7.4 SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.7.5 SMM Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.7.6 SMM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.7 SMI Generation for Virtual VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.8 SMM Service Routine Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.8.1 SMI Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.8.2 CPU States Related to SMM and Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . 90
HALT AND SHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.9.1 Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.9.2 I/O Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.9.3 Privilege Level Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.9.3.1 Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.9.4 Initialization and Transition to Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VIRTUAL 8086 MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.10.1 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.10.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.10.3 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.10.4 Entering and Leaving Virtual 8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
FLOATING POINT UNIT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.11.1 FPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.11.2 FPU Tag Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.11.3 FPU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.11.4 FPU Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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Featured Datasheets
Part Number | Description | MFRS |
30071-53 | The function is Geode GXLV Processor Series Low Power Integrated x86 Solutions. National Semiconductor | |
30071-53 | The function is Geode GXm Processor Integrated x86 Solution with MMX Support. National Semiconductor | |
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