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PDF CXD2508AR Data sheet ( Hoja de datos )
| Número de pieza | CXD2508AR | |
| Descripción | CD Digital Signal Processor | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2508AQ/AR
CD Digital Signal Processor
For the availability of this product, please contact the sales office.
Description
The CXD2508AQ/AR is a digital signal processor
for CD players and is equipped with built-in digital
filters, no-sound data detection circuit, and 1-bit
DAC.
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AQ
80 pin QFP (Plastic)
Features
DSP block
• Digital PLL
• EFM frame sync protection
• SEC strategy-based error correction
• Subcode demodulation, CRC checking
• Digital spindle servo
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AR
80 pin LQFP (Plastic)
• Servo auto sequencer
• Asymmetry compensation circuit
• Digital audio interface output
• 16K RAM
• Double-speed playback capability
• New microcomputer interface circuit
Digital filter, DAC block
• Double-speed playback capability
• Digital de-emphasis
• Digital attenuation
Applications
CD players
• No-sound data detection circuit
• 4 Fs oversampling filter
• Secondary ∆∑ noise shaper
Structure
Silicon gate CMOS IC
• PWM-system pulse conversion output
Absolute Maximum Ratings
Recommended Operating Conditions
• Supply voltage VDD Note) 4.5 to 5.5V
(double-speed playback)
3.5 to 5.5V
(normal-speed playback)
3.4 to 5.5V
(low power consumption
or special playback mode)
• Operating temperature
• Supply voltage VDD
–0.3 to 7.0
V
• Input voltage VI
–0.3 to 7.0
V
• Input voltage VIN Vss–0.3V (min.) VDD+0.3 (max.) V
• Output voltage VO
–0.3 to 7.0
V
• Storage temperature
Tstg –40 to 125 °C
• Supply voltage variation
VSS–AVSS –0.3V (min.) +0.3V (max.)
VDD–AVDD –0.3V (min.) +0.3V (max.)
Topr –20 (min.) 75 (max.) °C
Note) VDD (min.) is varied by the playback speed and built-in
VCO in the CXD2508AQ/AR. 4.5V is the value using the
VCO which generates the slower frequency in double-
speed playback. The table below shows the VDD (min.)
for each condition.
Playback
speed
VDD (min.) [V]
VCO
high-speed
VCO
normal-speed
DAC block
× 2 3.40 4.50 3.40
× 1 3.40 3.50 3.40
× 1∗ 3.40 3.40 3.40
∗ When the internal operation of the LSI is set to double-
speed mode and the crystal oscillation frequency is
halved, normal-speed playback results.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94602A54-ST
1 page  
CXD2508AQ/AR
Pin No.
RQ
33 35
34 36
35 37
36 38
37 39
38 40
39 41
40 42
41 43
42 44
43 45
44 46
45 47
46 48
47 49
48 50
49 51
50 52
51 53
52 54
53 55
54 56
55 57
56 58
57 59
58 60
59 61
60 62
61 63
62 64
63 65
64 66
65 67
66 68
Symbol
AVDD1
RF
BIAS
ASYI
ASYO
ASYE
WDCK
LRCK
LRCKI
PCMD
PCMDI
BCK
BCKI
GTOP
XUGF
XPCK
GFS
RFCK
VSS
C2PO
XROF
MNT3
MNT1
MNT0
FSTT
C4M
DOUT
EMPH
EMPHI
WFCK
ZEROL
ZEROR
DTS1
VDD
I/O Description
Analog power supply for DSP.
I EFM signal input.
I Constant current input of asymmetry compensation circuit.
I Comparator voltage input of asymmetry compensation circuit.
O EFM full-swing output (low = Vss, high = VDD).
I Low: asymmetry compensation off; high: asymmetry compensation on.
O D/A interface for 48-bit slot. Word clock (2Fs).
O D/A interface for 48-bit slot. LR clock (Fs).
I LR clock input for DAC. (48-bit slot)
O D/A interface. Serial data (two's complement, MSB first).
I Audio data input for DAC. (48-bit slot)
O D/A interface. Bit clock.
I Bit clock input for DAC. (48-bit slot)
O GTOP output.
O XUGF output.
O XPLCK output.
O GFS output.
O RFCK output.
GND.
O C2PO output.
O XRAOF output.
O MNT3 output.
O MNT1 output.
O MNT0 output.
O 2/3 frequency-divider output for Pins 73 and 74.
O 4.2336MHz output.
O Digital Out output.
O
Outputs high signal when the playback disc has emphasis, low signal when no
emphasis.
I DAC de-emphasis on/off. High: on; low: off.
O WFCK (write frame clock) output.
O
No-sound data detection output; high when no sound data is detected.
(Left channel)
O
No-sound data detection output; high when no sound data is detected.
(Right channel)
I Test pin 1 for DAC; normally low.
Digital power supply for DAC.
–5–
5 Page 
CXD2508AQ/AR
Description of Functions
1. CPU Interface and Instructions
• CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.
CLOK
750ns or more
DATA
XLAT
D1 D2 D3 D0 D1 D2 D3
Data
Address
750ns or more
Registers 4 to E
Valid
300ns max
• Information on each address and the data is provided in Table 1-1.
• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
Note) When XLAT is low, EXCK and SQCK must be set high.
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD2508AR.PDF ] | |
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