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PDF CXD2458 Data sheet ( Hoja de datos )
| Número de pieza | CXD2458 | |
| Descripción | Timing Generator for Color LCD Panels | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2458AR
Timing Generator for Color LCD Panels
For the availability of this product, please contact the sales office.
Description
The CXD2458AR is a timing signal generator for
the color LCD panel LCX005BK/BKB, LCX009AK/
AKB, LCX024AK and LCX027AK drivers.
48 pin LQFP (Plastic)
Features
• Generates the color LCD panel LCX005BK/BKB,
LCX009AK/AKB, LCX024AK and LCX027AK drive
pulse
• Supports NTSC/PAL
• Supports 16:9 (WIDE) display (NTSC/PAL)
• Supports composite SYNC and separate SYNC
(XHD, XVD) input
• Standby function (low power consumption function)
• Supports right/left inverse display
• AC drive of LCD panels during no signal
• Generates timing signal of external sample-and-
hold circuit
• Generates line inversion and field inversion signals
• AFC circuit supporting static and dynamic fluctuations
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD VSS – 0.3 to +6.0 V
• Input voltage
VI VSS – 0.3 to VDD + 0.3 V
• Output voltage
VO VSS – 0.3 to VDD + 0.3 V
• Operating temperature Topr –20 to +85 °C
• Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage
VDD 2.7 to 3.3
• Operating temperature Topr –20 to +85
V
°C
Applications
Color LCD viewfinders, compact LCD projectors, etc.
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98218-PS
1 page  
CXD2458AR
Electrical Characteristics
DC Characteristics
Item
Symbol Measurement conditions
(VDD = 3.0V ± 10%, Topr = –20 to +85°C)
Min. Typ. Max. Unit Remarks
H level input voltage
L level input voltage
VIH
VIL
0.7VDD
V
∗1
0.3VDD V
H level input current
L level input current
IIH1 VI = VDD
IIL1 VI = 0V
1.0
–1.0
µA
∗2
µA
H level input current
L level input current
IIH2 VI = VDD
IIL2 VI = 0V
10 180 µA
∗3
–3.0 µA
H level input current
L level input current
IIH3 VI = VDD
IIL3 VI = 0V
3.0 µA
∗4
–10 –180 µA
L level output voltage
H level output voltage
VOL1
VOH1
IOL = 1mA
IOH = –250µA
2.6
0.2 V
∗5
V
L level output voltage
H level output voltage
VOL2
VOH2
IOL = 500µA
IOH = –125µA
2.6
0.2 V
∗6
V
L level output voltage
H level output voltage
VOL3
VOH3
IOL = 500µA
IOH = –250µA
2.6
0.2 V
∗7
V
Output leak current
IOZ At high impedance state –1.0
1.0 µA ∗8
Current consumption
VDD = 3.0V, STBY = H
IDD
VDD = 3.0V, STBY = L
12 mA
3 mA
∗1 All input pins.
∗2 Input pins XHD and CKI.
∗3 Input pins SLNP and XVD.
∗4 Input pins XCLR, RGT, STBY, HP4, TST3 and TST4.
∗5 Output pins HCK1 and HCK2.
∗6 All output pins other than those listed in ∗5, ∗7 and ∗8.
∗7 Output pin CKO. However, set the input level of input pin CKI to 0V or VDD during measurement.
∗8 Output pin RPD.
AC Characteristics
(VDD = 3.0V ± 10%, Topr = –20 to +85°C)
Item
Clock input cycle
Applicable pins
CKI
Symbol Conditions Min. Typ. Max. Unit
tck 60 ns
Cross-point time difference
HCK1, HCK2
VCK1, VCK2
CL = 30pF 1
∆t
CL = 30pF 3
15 ns
20 ns
Output rise delay time
VCKn, HCKn
tpr
Other than HCKn and VCKn
CL = 30pF
CL = 30pF
84 ns
76 ns
Output fall delay time
VCKn, HCKn
tpf
Other than HCKn and VCKn
CL = 30pF
CL = 30pF
71 ns
62 ns
HCK1, SH1 delay time difference HCK1, SH1
dt1 CL = 30pF 1
5 ns
HCK2, SH1 delay time difference HCK2, SH1
dt2 CL = 30pF 1
5 ns
HCK Duty
HCK1, HCK2
dtyH CL = 30pF 48
53 %
–5–
5 Page 
CXD2458AR
Right/Left Inverse Display
The CXD2458AR outputs a right/left inversion timing pulse that supports the right/left inverse display function
of the LCX005BK/BKB, LCX024AK, LCX009AK/AKB and LCX027AK.
The LCD panel is arranged in a delta pattern, where the same signal line is 1.5-dot offset at adjoining vertical
lines. For this reason, a 1.5-dot offset is attached to the horizontal start pulse (HST) of the LCD between odd
lines and even lines in order to correct this difference. Other H system output pulses are also 1.5-dot offset.
When the panel is driven with left scan (Reverse scan), this offset relationship becomes inverted for even and
odd lines, and the asymmetrical dot arrangement produces an offset.
Therefore, the CXD2458AR internally controls the right/left and interline offset to allow right scan or left scan
display by setting RGT = H or L for right/left inversion.
Right scan
(Normal scan)
Left scan
(Reverse scan)
H SCANNER
Display area
SH Pulse and HCK Phase Relationship
The phase relationship between the SH pulse and HCK changes according to switching between right scan
(Normal scan) and left scan (Reverse scan). SH3 is the re-sampling pulse.
RGT = H (Normal scan)
RGT = L (Reverse scan)
HCK1/2
SH1
SH2
SH3
SH4
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD2458.PDF ] | |
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