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PDF CXD2412AQ Data sheet ( Hoja de datos )
| Número de pieza | CXD2412AQ | |
| Descripción | Timing Generator for LCD Panels | |
| Fabricantes | Sony Corporation | |
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CXD2412AQ
Timing Generator for LCD Panels
Description
The CXD2412AQ is a timing signal generator for
LCD panel drivers.
Features
• Generates the LCX007 drive pulse.
• Supports NTSC/PAL.
(With PAL, a video signal on which scanning line
conversion has been performed is used.)
• Supports WIDE.
• Supports HD (20 MHz band).
• Supports Muse-NTSC conversion signal (MNDC).
• Supports up/down and/or right/left inversion.
• Supports three-panel projector.
• Generates timing signal of external sample-and-
hold circuit.
• Generates line inversion and field inversion
signals.
• AC drive for LCD panel during no signal.
• AFC circuit supporting static and dynamic
fluctuations.
Applications
LCD projectors
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25 °C)
• Supply voltage
VDD VSS–0.5 to +7.0 V
• Input voltage
VI VSS – 0.5 to VDD + 0.5 V
• Output voltage
VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage
VDD 5.0 ± 0.5
• Operating temperature Topr –20 to +75
V
°C
100 pin QFP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94Y04-ST
1 page  
Pin No. Symbol I/O
Description
75 SLFR
I
Switches between H inversion and F inversion
(H: H inversion / L: F inversion)
76 NTPL I Switches mode
77 XWD
I Switches mode
78 VDD5
— Power supply
79 VSS8
— GND
80 XHD
I Switches mode
81 SLSH3 I Switches SH
82 TC2
I FPD2 pin pulse width adjustment
83 FPD2 O Phase comparator output B-2 (for WIDE)
84 PEO2 O Loop filter integrator output 2
85 PWM2 I Loop filter integrator input 2
86 RPD2 O Phase comparator output A-2 (for WIDE)
87 VSS10 — GND
88 CKO2 O WIDE oscillation cell output
89 CKI2
I WIDE oscillation cell input
90 VSS11 — GND
91 CKO3 O HD/MNDC oscillation cell output
92 CKI3
I HD/MNDC oscillation cell input
93 VSS12 — GND
94 RPD3 O Phase comparator output A-3 (for HD/MNDC)
95 PEO3 O Loop filter integrator output 3
96 PWM3 I Loop filter integrator input 3
97 FPD3 O Phase comparator output B-3 (for HD/MNDC)
98 TC3
I FPD3 pin pulse width adjustment
99 CP1
I Switches pedestal clamp position
100 CP2
I Switches pedestal clamp position
CXD2412AQ
Input pin for open
status
H
H
H
H
L
H
L
–5–
5 Page 
Mode Selection
Mode selection is performed by means of three pins, as shown in the table.
NTPL
XWD
XHD
Mode
HH H
NTSC
LHH
PAL
H L H NTSC WIDE
LLH
PAL+
LX L
HD
HX
L
MNDC
CXD2412AQ
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD2412AQ.PDF ] | |
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