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Número de pieza | CXD2411AR | |
Descripción | Timing Generator for Color LCD Panels | |
Fabricantes | Sony Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CXD2411AR (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! CXD2411AR
Timing Generator for Color LCD Panels
For the availability of this product, please contact the sales office.
Description
The CXD2411AR is a timing signal generator for
48 pin LQFP (Plastic)
color LCD panel drivers.
Features
• Generates the LCX005BK/BKB and
LCX009AK/AKB drive pulse.
• Supports right/left inverse display.
• Supports 16:9 wide display.
• Supports CSYNC and Separate SYNC (XHD, XVD)
input.
• Supports line inversion and field inversion.
• AC drive for LCD panel during no signal
(NTSC/PAL).
• Generates timing signal of external sample-and-
hold circuit.
• AFC circuit supporting static and dynamic
fluctuations.
Applications
• Color LCD viewfinder
• Single-panel and three-panel projectors
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD VSS – 0.5 to +7.0 V
• Input voltage
VI VSS – 0.5 to VDD + 0.5 V
• Output voltage VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature
Topr
–20 to +85
°C
• Storage temperature
Tstg –55 to +150
°C
Recommended Operating Conditions
• Supply voltage VDD
2.7 to 5.5
• Operating temperature
Topr
–20 to +85
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95Z14-ST
1 page CXD2411AR
Electrical Characteristics
1. DC characteristics
(Temperature = 25°C, VSS = 0V)
Item Symbol
Conditions
Min.
Supply voltage
VDD
2.7
Input voltage
VIH TTL input cell (5V ±10%)
2.2
Input voltage
VIH TTL input cell (3.0V ±10%)
1.8
Input voltage
VIL TTL input cell
Input voltage
VIH CMOS input cell
0.7VDD
Input voltage
VIL CMOS input cell
Output voltage
VOH IOH = –4mA (HCKn, VCKn)
VDD – 0.8
Output voltage
VOL IOL = 8mA (HCKn, VCKn)
Output voltage
VOH IOH = –3mA (CKO, CKI)
VDD/2
Output voltage
VOL IOL = 3mA (CKO, CKI)
Output voltage
VOH IOH = –2mA (other than the above)
VDD – 0.8
Output voltage
VOL IOL = 4mA (other than the above)
Input leak current IL
Normal input pin
–10
Input leak current IIL
With pull-up resistor
–12
Input leak current IIH
With pull-down resistor
12
Output leak current ILZ
RPDn, FPDn (at high impedance state) –40
Current consumption IDD
VDD = 5.0V
Typ.
–100
100
25
Max. Unit
5.5 V
V
V
0.8 V
V
0.3VDD V
V
0.4 V
V
VDD/2 V
V
0.4 V
10 µA
–240 µA
240 µA
40 µA
mA
2. AC characteristics
Item
Applicable pins
Symbol
Clock input cycle
CKI
Cross-point time difference HCK1, HCK2
Cross-point time difference VCK1, VCK2
∆t
∆t
Output rise delay
HCKn, VCKn
tpr
Output fall delay
HCKn, VCKn
tpf
Output rise delay
Other than HCKn and VCKn tpr
Output fall delay
Other than HCKn and VCKn tpf
HCK1, SH1 delay time
difference
HCK1, SH1
dt1
HCK1, SH1 delay time
difference
HCK1, SH1
dt2
HCK2, SH1 delay time
difference
HCK2, SH1
dt1
HCK2, SH1 delay time
difference
HCK2, SH1
dt2
HCK1 Duty
HCK1
tH/tH + tL
HCK2 Duty
HCK2
tH/tH + tL
Note) n = 1, 2
–5–
(VDD = 2.7 to 5.5V)
Conditions Min. Typ. Max. Unit
60 ns
CL = 30pF
10 ns
CL = 30pF
10 ns
CL = 30pF
30 ns
CL = 30pF
25 ns
CL = 30pF
40 ns
CL = 30pF
22 ns
CL = 30pF 60
85 ns
CL = 30pF 60
95 ns
CL = 30pF 60
85 ns
CL = 30pF 60
CL = 30pF 46
CL = 30pF 46
95 ns
52 %
52 %
5 Page CXD2411AR
LCX009AK/AKB (NTSC, PAL)
HP4 HP3 HP2 HP1
HST1 (NTSC/PAL)
0 0 0 0 91fh (5.51/5.55µs)
HST2 (NTSC/PAL)
93.5fh (5.66/5.70µs)
0 0 0 1 89fh
91.5fh
0 0 1 0 87fh
89.5fh
0 0 1 1 85fh
87.5fh
0 1 0 0 83fh
85.5fh
0 1 0 1 81fh
83.5fh
0 1 1 0 79fh
81.5fh
0 1 1 1 77fh
79.5fh
1 0 0 0 75fh (4.54/4.57µs)
77.5fh (4.69/4.72µs)
1 0 0 1 73fh
75.5fh
1 0 1 0 71fh
73.5fh
1 0 1 1 69fh
71.5fh
1 1 0 0 67fh
69.5fh
1 1 0 1 65fh
67.5fh
1 1 1 0 63fh
65.5fh
1 1 1 1 61fh (3.69/3.72µs)
63.5fh (3.84/3.87µs)
∗ The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above
timings. (Refer to the Timing Charts for details.)
– 11 –
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet CXD2411AR.PDF ] |
Número de pieza | Descripción | Fabricantes |
CXD2411AR | Timing Generator for Color LCD Panels | Sony Corporation |
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