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PDF CXD1812Q Data sheet ( Hoja de datos )
| Número de pieza | CXD1812Q | |
| Descripción | ATAPI I/F CD-ROM DECODER | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD1812Q/R
ATAPI I/F CD-ROM DECODER
For the availability of this product, please contact the sales office.
Description
The CXD1812Q/R is a CD-ROM decoder LSI with
a built-in ATAPI I/F.
CXD1812Q
100 pin QFP (Plastic)
CXD1812R
100 pin LQFP (Plastic)
Features
• Compatible with CD-ROM, CD-I and CD-ROM XA
formats
• Real time error correction
• Automatic multi-block transfer function
• Readable Subcode-Q data by byte from the Sub
CPU
• Capable of transferring up to double speed
playback and Mode2 when the 33.8688 MHz clock
is used
Transfer in Mode3 is possible when the decoder is
OFF (The transfer speed depends on playback
speed and clock frequency.)
• Supports PIO/single-word DMA/multiword DMA
data transfer mode
• IORDY support available
• Automatic reception of PACKET commands
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD –0.5 to +7.0
• Input voltage
VI –0.5 to VDD +0.5
• Output voltage
VO –0.5 to VDD +0.5
• Operating temperature Topr
–20 to +75
• Storage temperature
Tstg
–55 to +150
V
V
V
°C
°C
Recommended Operating Conditions
• Supply voltage
VDD 4.5 to 5.5 (+5.0 typ.)
• Operating temperature Topr
–20 to +75
V
°C
Applications
CD-ROM drives
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95233-ST
1 page  
CXD1812Q/R
Pin No.
Symbol I/O
QFP LQFP
Description
37 35 MA8
O DRAM address
38 36 MA9
O DRAM address (MSB)
39 37 XRAS O DRAM row address strobe negative logic signal
40 38 GND
— Ground
41 39 XCAS O DRAM column address strobe negative logic signal
42 40 XMWR O DRAM write enable negative logic signal
43 41 MDB0 I/O DRAM data bus (LSB)
44 42 MDB1 I/O DRAM data bus
45 43 MDB2 I/O DRAM data bus
46 44 MDB3 I/O DRAM data bus
47 45 GND
— Ground
48 46 MDB4 I/O DRAM data bus
49 47 MDB5 I/O DRAM data bus
50 48 MDB6 I/O DRAM data bus
51 49 MDB7 I/O DRAM data bus (MSB)
52 50 DASP I/O Drive active/slave present negative logic signal; open drain output
53 51 VDD
— Power supply
54 52 GND
— Ground
55 53 HCS1 I Chip select negative logic signal from host
56 54 HCS0 I Chip select negative logic signal from host
57 55 HA2
I Host address (MSB)
58 56 HA0
I Host address (LSB)
59 57 XPDI I/O Passed diagnostics negative logic signal; open drain output
60 58 HA1
I Host address
61 59 XS16 O 16-bit I/O port select negative logic signal; open drain output
62 60 HINT
O Interrupt request positive logic signal to host
63 61 XHAC I DMA acknowledge negative logic signal from host
64 62 REDY O I/O channel ready positive logic signal; open drain output
65 63 GND
— Ground
66 64 XHRD I Strobe negative logic signal for reading data from host
67 65 XHWR I Strobe negative logic signal for writing data from host
68 66 HDRQ O DMA request positive logic signal to host
69 67 HDBF I/O Host data bus (MSB)
70 68 HDB0 I/O Host data bus (LSB)
71 69 HDBE I/O Host data bus
72 70 HDB1 I/O Host data bus
–5–
5 Page 
2-3. HOST Interface
(1) PIO
HCS0, 1
HA0 to 2
XS16
XHRD
XHWR
HDB0 to F
REDY
Txsl
Trww
Tas
Tdd
Tah Tas
Tdf
Trww
Tah
Tds Tdh
Trel Trel
CXD1812Q/R
Item
Address setup time (for XHRD/XHWR ↓)
Address hold time (for XHRD/XHWR ↑)
XHRD/XHWR pulse width
Data delay time (for XHRD ↓)
Data float time (for XHRD ↑)
Data setup time (for XHWR ↑)
Data hold time (for XHWR ↑)
XS16 fall time (for Address valid)
REDY fall time (for XHRD/XHWR ↓)
Symbol Min. Typ. Max. Unit
Tas 20
ns
Tah 5
ns
Trww
50
ns
Tdd 26 ns
Tdf 5
21 ns
Tds 20
ns
Tdh 5
ns
Txsl 8 ns
Trel 14 ns
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD1812Q.PDF ] | |
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