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PDF CY7B991 Data sheet ( Hoja de datos )
| Número de pieza | CY7B991 | |
| Descripción | Programmable Skew Clock Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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92
CY7B991
CY7B992
Programmable Skew Clock Buffer
Features
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 80-MHz output operation
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at 1⁄2 and 1⁄4 input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input to output delay
• 50% duty-cycle outputs
• Outputs drive 50Ω terminated lines
• Low operating current
• 32-pin PLCC/LCC package
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
• Compatible with a Pentium™-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Logic Block Diagram
Pin Configuration
TEST
FB
REF
PHASE
FREQ FILTER
DET
FS
VCO AND
TIME UNIT
GENERATOR
4F0
4F1
SELECT
INPUTS
(THREE
LEVEL)
3F0
3F1
2F0
2F1
SKEW
SELECT
MATRIX
PLCC/LCC
4 3 2 1 32 31 30
3F1 5
29 2F0
4Q0 4F0 6
28 GND
4F1 7
27 1F1
4Q1
VCCQ 8
26 1F0
3Q0
VCCN 9
CY7B991
CY7B992
25 VCCN
4Q1 10
3Q1
4Q0 11
24 1Q0
23 1Q1
2Q0 GND 12
22 GND
GND 13
21 GND
2Q1 14 15 16 17 18 19 20
1F0
1F1
Pentium is a trademark of Intel Corporation.
7B991–1
1Q0
1Q1
7B991–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07138 Rev. **
Revised September 26, 2001
1 page  
CY7B991
CY7B992
Capacitance[12]
Parameter
Description
Test Conditions
Max.
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 5.0V
10
Note:
12. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
Unit
pF
AC Test Loads and Waveforms
5V
R1 R1=130
R2=91
CL = 50 pF (CL =30 pF for –2 and –5 devices)
CL R2 (Includes fixture and probe capacitance)
7B991–4
TTL AC Test Load (CY7B991)
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
2.0V
Vth =1.5V
0.8V
≤1ns
≤1ns
7B991–5
TTL Input Test Waveform (CY7B991)
VCC
R1=100
R1
R2=100
CL = 50 pF (CL =30 pF for –2 and –5 devices)
(Includes fixture and probe capacitance)
CL R2
7B991–6
CMOS AC Test Load (CY7B992)
VCC
80%
Vth = VCC/2
20%
0.0V
80%
Vth = VCC/2
20%
≤3ns
≤3ns
7B991–7
CMOS Input Test Waveform (CY7B992)
Document #: 38-07138 Rev. **
Page 5 of 15
5 Page 
CY7B991
CY7B992
3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx
skews to +6 tU, a total of +10 tU skew is realized.) Many other con-
figurations can be realized by skewing both the output used as the
FB input and skewing the other outputs.
REF
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1F0 1Q0
1F1 1Q1
TEST
7B991–11
Figure 4. Inverted Output Connections
Figure 4 shows an example of the invert function of the PSCB.
In this example the 4Q0 output used as the FB input is pro-
grammed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q out-
puts to become the “inverted” outputs with respect to the REF
input. By selecting which output is connect to FB, it is possible
to have 2 inverted and 6 non-inverted outputs or 6 inverted and
2 non-inverted outputs. The correct configuration would be de-
termined by the need for more (or fewer) inverted outputs. 1Q,
2Q, and 3Q outputs can also be skewed to compensate for
varying trace delays independent of inversion on 4Q.
REF
20 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
40 MHz
20 MHz
80 MHz
7B991–12
Figure 5. Frequency Multiplier with Skew Connections
Figure 5 illustrates the PSCB configured as a clock multiplier.
The 3Q0 output is programmed to divide by four and is fed
back to FB. This causes the PLL to increase its frequency until
the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx
and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, which results in a 40-MHz wave-
form at these outputs. Note that the 20- and 40-MHz clocks fall
simultaneously and are out of phase on their rising edge. This
will allow the
quency and
designer to use the rising edges of the
1⁄4 frequency outputs without concern
1⁄2
for
fre-
ris-
ing-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at
80 MHz and are skewed by programming their select inputs
accordingly. Note that the FS pin is wired for 80-MHz operation
because that is the frequency of the fastest output.
REF
20 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
10 MHz
5 MHz
20 MHz
1F0 1Q0
1F1 1Q1
TEST
7B991–13
Figure 6. Frequency Divider Connections
Figure 6 demonstrates the PSCB in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
outputs are aligned. This allows use of the rising edges of the
1⁄2 frequency and 1⁄4 frequency without concern for skew
mismatch. The 1Qx outputs are programmed to zero skew and
are aligned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15- to 30-MHz range
since the highest frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on
the 3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An invert-
ed output allows the system designer to clock different sub-
systems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function allows
the two subsystems to each be clocked 180 degrees out of
phase, but still to be aligned within the skew spec.
The divided outputs offer a zero-delay divider for portions of
the system that need the clock to be divided by either two or
four, and still remain within a narrow skew of the “1X” clock.
Without this feature, an external divider would need to be add-
ed, and the propagation delay of the divider would add to the
skew between the different clock signals.
These divided outputs, coupled with the Phase Locked Loop,
allow the PSCB to multiply the clock rate at the REF input by
either two or four. This mode will enable the designer to dis-
tribute a low-frequency clock between various portions of the
system, and then locally multiply the clock rate to a more suit-
able frequency, while still maintaining the low-skew character-
istics of the clock driver. The PSCB can perform all of the func-
tions described above at the same time. It can multiply by two
and four or divide by two (and four) at the same time that it is
shifting its outputs over a wide range or maintaining zero skew
between selected outputs.
Document #: 38-07138 Rev. **
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY7B991.PDF ] | |
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