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PDF CY8C26643 Data sheet ( Hoja de datos )
| Número de pieza | CY8C26643 | |
| Descripción | Configurable Mixed-Signal Array with On-board Controller | |
| Fabricantes | Cypress Semiconductor | |
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CY8C25122, CY8C26233, CY8C26443, CY8C26643
Device Data Sheet for Silicon Revision D
8-Bit Programmable System-on-Chip (PSoC™) Microcontrollers
September 5, 2002
CYPRESS MICROSYSTEMS
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
1
1 page  
Table of Contents
1.0 Functional Overview ......................................................................................................................14
1.1 Key Features ..............................................................................................................................14
1.2 Pin-out Descriptions ...................................................................................................................15
2.0 CPU Architecture ............................................................................................................................19
2.1 Introduction ................................................................................................................................19
2.2 CPU Registers ...........................................................................................................................20
2.3 Addressing Modes .....................................................................................................................21
2.4 Instruction Set Summary ...........................................................................................................25
3.0 Memory Organization .....................................................................................................................26
3.1 Flash Program Memory Organization ........................................................................................26
3.2 RAM Data Memory Organization ...............................................................................................26
4.0 Register Organization ....................................................................................................................26
4.1 Introduction ................................................................................................................................26
4.2 Register Bank 0 Map .................................................................................................................27
4.3 Register Bank 1 Map ................................................................................................................28
5.0 I/O Ports ...........................................................................................................................................29
5.1 Introduction ................................................................................................................................29
6.0 I/O Registers ...................................................................................................................................31
6.1 Port Data Registers ...................................................................................................................31
6.2 Port Interrupt Enable Registers .................................................................................................31
6.3 Port Global Select Registers .....................................................................................................32
7.0 Clocking ..........................................................................................................................................35
7.1 Oscillator Options .......................................................................................................................35
7.2 System Clocking Signals ............................................................................................................38
8.0 Interrupts .........................................................................................................................................42
8.1 Overview ....................................................................................................................................42
8.2 Interrupt Control Architecture .....................................................................................................44
8.3 Interrupt Vectors .........................................................................................................................44
8.4 Interrupt Masks ..........................................................................................................................45
8.5 Interrupt Vector Register ...........................................................................................................46
8.6 GPIO Interrupt ............................................................................................................................47
9.0 Digital PSoC Blocks .......................................................................................................................48
9.1 Introduction ................................................................................................................................48
9.2 Digital PSoC Block Bank 1 Registers .........................................................................................49
9.3 Digital PSoC Block Bank 0 Registers .........................................................................................54
9.4 Global Inputs and Outputs .........................................................................................................60
9.5 Available Programmed Digital Functionality ...............................................................................60
10.0 Analog PSoC Blocks ....................................................................................................................71
10.1 Introduction ..............................................................................................................................71
10.2 Analog System Clocking Signals .............................................................................................72
10.3 Array of Analog PSoC Blocks .................................................................................................72
10.4 Analog Reference and Bias Control .........................................................................................73
10.5 AGND, REFHI, REFLO ............................................................................................................73
10.6 Analog PSoC Block Clocking Options ......................................................................................74
10.7 Analog Clock Select Register ..................................................................................................75
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
5
5 Page 
List of Figures
Figure 1: Block Diagram ............................................................................................................................13
Figure 2: CY8C25122 ................................................................................................................................15
Figure 3: CY8C26233 ................................................................................................................................15
Figure 4: 26443 PDIP/SOIC/SSOP ...........................................................................................................16
Figure 5: 26643 TQFP ...............................................................................................................................17
Figure 6: 26643 PDIP/SSOP .....................................................................................................................18
Figure 7: General Purpose I/O Pins ..........................................................................................................30
Figure 8: External Crystal Oscillator Connections .....................................................................................37
Figure 9: PSoC MCU Clock Tree of Signals ..............................................................................................39
Figure 10: Interrupts Overview ..................................................................................................................43
Figure 11: GPIO Interrupt Enable Diagram ...............................................................................................47
Figure 12: Digital Basic and Digital Communications PSoC Blocks ..........................................................49
Figure 13: Polynomial LFSR ......................................................................................................................65
Figure 14: Polynomial PRS .......................................................................................................................65
Figure 15: SPI Waveforms ........................................................................................................................68
Figure 16: Array of Analog PSoC Blocks ...................................................................................................72
Figure 17: NMux Connections ...................................................................................................................76
Figure 18: PMux Connections ...................................................................................................................77
Figure 19: RBotMux Connections ..............................................................................................................77
Figure 20: Analog Continuous Time PSoC Blocks ....................................................................................79
Figure 21: Analog Switch Cap Type A PSoC Blocks .................................................................................84
Figure 22: AMux Connections ...................................................................................................................85
Figure 23: CMux Connections ...................................................................................................................85
Figure 24: BMuxSCA/SCB Connections ...................................................................................................86
Figure 25: Analog Switch Cap Type B PSoC Blocks .................................................................................93
Figure 26: Analog Input Muxing ...............................................................................................................101
Figure 27: Analog Output Buffers ............................................................................................................103
Figure 28: Multiply/Accumulate Block Diagram .......................................................................................108
Figure 29: Decimator Coefficients ...........................................................................................................110
Figure 30: Execution Reset .....................................................................................................................113
Figure 31: Three Sleep States .................................................................................................................115
Figure 32: Switch Mode Pump ................................................................................................................117
Figure 33: Programming Wave Forms ....................................................................................................122
Figure 34: PSoC Designer Functional Flow ............................................................................................123
Figure 35: CY8C25xxx/CY8C26xxx Voltage Frequency Graph ..............................................................125
Figure 36: 44-Lead Thin Plastic Quad Flat Pack A44 .............................................................................141
Figure 37: 20-Pin Shrunk Small Outline Package O20 ...........................................................................142
Figure 38: 28-Lead (210-Mil) Shrunk Small Outline Package O28 .........................................................143
Figure 39: 48-Lead Shrunk Small Outline Package O48 .........................................................................143
Figure 40: 20-Lead (300-Mil) Molded DIP P5 ..........................................................................................144
Figure 41: 28-Lead (300-Mil) Molded DIP P21 ........................................................................................144
Figure 42: 48-Lead (600-Mil) Molded DIP P25 ........................................................................................144
Figure 43: 20-Lead (300-Mil) Molded SOIC S5 .......................................................................................145
Figure 44: 28-Lead (300-Mil) Molded SOIC S21 .....................................................................................145
Figure 45: 8-Lead (300-Mil) Molded DIP .................................................................................................146
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C26643.PDF ] | |
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