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PDF CY8C26443 Data sheet ( Hoja de datos )

Número de pieza CY8C26443
Descripción 8-Bit Programmable System-on-Chip (PSoC) Microcontrollers
Fabricantes Cypress Semiconductor　
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CY8C26443 Hoja de datos, Descripción, Manual

Configurable
Mixed-Signal Array
with On-board Controller
CY8C25122, CY8C26233, CY8C26443, CY8C26643
Device Data Sheet for Silicon Revision D
Programmable System-on-Chip (PSoC™)
August 18, 2003
CYPRESS MICROSYSTEMS
Document #: 38-12010 CY Rev. *B CMS Rev. 3.22
1

1 page




CY8C26443 pdf
Table of Contents
1.0 Functional Overview ......................................................................................................................14
1.1 Key Features ..............................................................................................................................14
1.2 Pin-out Descriptions ...................................................................................................................15
2.0 CPU Architecture ............................................................................................................................19
2.1 Introduction ................................................................................................................................19
2.2 CPU Registers ...........................................................................................................................20
2.3 Addressing Modes .....................................................................................................................21
2.4 Instruction Set Summary ...........................................................................................................25
3.0 Memory Organization .....................................................................................................................26
3.1 Flash Program Memory Organization ........................................................................................26
3.2 RAM Data Memory Organization ...............................................................................................26
4.0 Register Organization ....................................................................................................................26
4.1 Introduction ................................................................................................................................26
4.2 Register Bank 0 Map .................................................................................................................27
4.3 Register Bank 1 Map ................................................................................................................28
5.0 I/O Ports ...........................................................................................................................................29
5.1 Introduction ................................................................................................................................29
6.0 I/O Registers ...................................................................................................................................31
6.1 Port Data Registers ...................................................................................................................31
6.2 Port Interrupt Enable Registers .................................................................................................31
6.3 Port Global Select Registers .....................................................................................................32
7.0 Clocking ..........................................................................................................................................35
7.1 Oscillator Options .......................................................................................................................35
7.2 System Clocking Signals ............................................................................................................38
8.0 Interrupts .........................................................................................................................................42
8.1 Overview ....................................................................................................................................42
8.2 Interrupt Control Architecture .....................................................................................................44
8.3 Interrupt Vectors .........................................................................................................................44
8.4 Interrupt Masks ..........................................................................................................................45
8.5 Interrupt Vector Register ...........................................................................................................46
8.6 GPIO Interrupt ............................................................................................................................47
9.0 Digital PSoC Blocks .......................................................................................................................48
9.1 Introduction ................................................................................................................................48
9.2 Digital PSoC Block Bank 1 Registers .........................................................................................49
9.3 Digital PSoC Block Bank 0 Registers .........................................................................................54
9.4 Global Inputs and Outputs .........................................................................................................60
9.5 Available Programmed Digital Functionality ...............................................................................60
10.0 Analog PSoC Blocks ....................................................................................................................71
10.1 Introduction ..............................................................................................................................71
10.2 Analog System Clocking Signals .............................................................................................72
10.3 Array of Analog PSoC Blocks .................................................................................................72
10.4 Analog Reference Control ........................................................................................................73
10.5 Analog PSoC Block Clocking Options ......................................................................................76
10.6 Analog Clock Select Register ..................................................................................................77
10.7 Analog Continuous Time PSoC Blocks ....................................................................................80
August 18, 2003
Document #: 38-12010 CY Rev. *B CMS Rev. 3.22
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CY8C26443 arduino
List of Figures
Figure 1: Block Diagram ............................................................................................................................ 13
Figure 2: CY8C25122 ................................................................................................................................ 15
Figure 3: CY8C26233 ................................................................................................................................ 15
Figure 4: 26443 PDIP/SOIC/SSOP ...........................................................................................................16
Figure 5: 26643 TQFP ............................................................................................................................... 17
Figure 6: 26643 PDIP/SSOP ..................................................................................................................... 18
Figure 7: General Purpose I/O Pins .......................................................................................................... 30
Figure 8: External Crystal Oscillator Connections ..................................................................................... 37
Figure 9: PSoC MCU Clock Tree of Signals ..............................................................................................39
Figure 10: Interrupts Overview .................................................................................................................. 43
Figure 11: GPIO Interrupt Enable Diagram ............................................................................................... 47
Figure 12: Digital Basic and Digital Communications PSoC Blocks .......................................................... 49
Figure 13: Polynomial LFSR ...................................................................................................................... 65
Figure 14: Polynomial PRS ....................................................................................................................... 65
Figure 15: SPI Waveforms ........................................................................................................................ 68
Figure 16: Array of Analog PSoC Blocks ................................................................................................... 72
Figure 17: Analog Reference Control Schematic ...................................................................................... 73
Figure 18: NMux Connections ................................................................................................................... 78
Figure 19: PMux Connections ................................................................................................................... 79
Figure 20: RBotMux Connections .............................................................................................................. 79
Figure 21: Analog Continuous Time PSoC Blocks .................................................................................... 81
Figure 22: Analog Switch Cap Type A PSoC Blocks ................................................................................. 86
Figure 23: AMux Connections ................................................................................................................... 87
Figure 24: CMux Connections ................................................................................................................... 87
Figure 25: BMuxSCA/SCB Connections ................................................................................................... 88
Figure 26: Analog Switch Cap Type B PSoC Blocks ................................................................................. 95
Figure 27: Analog Input Muxing ...............................................................................................................103
Figure 28: Analog Output Buffers ............................................................................................................105
Figure 29: Multiply/Accumulate Block Diagram .......................................................................................110
Figure 30: Decimator Coefficients ...........................................................................................................112
Figure 31: Execution Reset .....................................................................................................................115
Figure 32: Three Sleep States .................................................................................................................117
Figure 33: Switch Mode Pump ................................................................................................................119
Figure 34: Programming Wave Forms ....................................................................................................124
Figure 35: PSoC Designer Functional Flow ............................................................................................125
Figure 36: CY8C25xxx/CY8C26xxx Voltage Frequency Graph ..............................................................127
Figure 37: 44-Lead Thin Plastic Quad Flat Pack A44 .............................................................................143
Figure 38: 20-Pin Shrunk Small Outline Package O20 ...........................................................................144
Figure 39: 28-Lead (210-Mil) Shrunk Small Outline Package O28 .........................................................145
Figure 40: 48-Lead Shrunk Small Outline Package O48 .........................................................................145
Figure 41: 20-Lead (300-Mil) Molded DIP P5 ..........................................................................................146
Figure 42: 28-Lead (300-Mil) Molded DIP P21 ........................................................................................146
Figure 43: 48-Lead (600-Mil) Molded DIP P25 ........................................................................................146
Figure 44: 20-Lead (300-Mil) Molded SOIC S5 .......................................................................................147
Figure 45: 28-Lead (300-Mil) Molded SOIC S21 .....................................................................................147
August 18, 2003
Document #: 38-12010 CY Rev. *B CMS Rev. 3.22
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