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PDF CY7C68300 Data sheet ( Hoja de datos )

Número de pieza CY7C68300
Descripción EZ-USB AT2 USB 2.0 to ATA/ATAPI Bridge
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CY7C68300 Hoja de datos, Descripción, Manual

CY7C68300
CY7C68300
EZ-USB AT2™
USB 2.0 to ATA/ATAPI Bridge
Document #: 38-08011 Rev. *B
Page 1 of 26

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CY7C68300 pdf
CY7C68300
SCL
SDA
I2C-Compatible
Bus Controller
24
MHz
XTAL
VBUS
D+
D-
PLL
USB 2.0 XCVR
AT2 Internal Logic
ATA_EN (ATA Interface 3-state)
ATA Interface
Control Signals
Control
ATA
Interface 16 Bit ATA Data
Logic
CY Smart USB
FS/HS Engi ne
4kByte FIFO
Data
Figure 1-1. Block Diagram
Document #: 38-08011 Rev. *B
Page 5 of 26

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CY7C68300 arduino
CY7C68300
4.0 Functional Overview
4.1 USB Signaling Speed
EZ-USB AT2 operates at two of the three rates defined in the USB Specification Revision 2.0 dated April 27, 2000:
Full speed, with a signaling bit rate of 12 Mbits/sec
High speed, with a signaling bit rate of 480 Mbits/sec.
EZ-USB AT2 does not support the low-speed signaling rate of 1.5 Mbits/sec.
4.2 ATA Interface
The ATA/ATAPI port on the EZ-USB AT2 is compliant with the Information Technology AT Attachment with Packet Interface 6
(ATA/ATAPI-6) Specification, T13/1410D Rev 3B. The EZ-USB AT2 supports both ATAPI packet commands over USB.
Additionally, the EZ-USB AT2 translates ATAPI SFF-8070i commands to ATA commands for seamless integration of ATA devices
with generic Mass Storage Class BOT drivers.
5.0 Enumeration
During the power-up sequence, internal logic checks the I2C-compatible port for an EEPROM whose first two bytes are both
0x4D. If a valid signature is found, the EZ-USB AT2 uses the values stored in the EEPROM to configure the USB descriptors for
normal operation. If an invalid EEPROM signature is read, or if no EEPROM is detected, the EZ-USB AT2 defaults into Board
Manufacturing Test Mode. The two modes of operation are described in subsections 5.1 and 5.2, below.
5.1 Board Manufacturing Test Mode
In Board Manufacturing Test Mode, the chip behaves as a USB 2.0 device but the ATA/ATAPI interface is not active. The EZ-USB
AT2 allows for reading and writing an EEPROM and for board level testing through vendor specific ATAPI commands utilizing the
CBW Command Block as described in the USB Mass Storage Class Bulk-Only Transport Specification. There is a vendor-specific
ATAPI command for the EEPROM access (CfgCB) and one for the board level testing (MfgCB).
5.1.1 CfgCB
The cfg_load and cfg_read vendor-specific commands are passed down through the bulk pipe in the CBWCB portion of the CBW.
The format of this CfgCB is shown below. Byte 0 will be a vendor-specific command designator whose value is configurable and
set in the configuration data (EEPROM address 0x04). Byte 1 must be set to 0x26 to identify CfgCB. Byte 2 is reserved and must
be set to zero. Byte 3 is used to determine the memory source to write/read. For the EZ-USB AT2, this byte must be set to 0x02,
meaning the EEPROM. Bytes 4 and 5 will be used to determine the start address. For the EZ-USB AT2, this must always be
0x0000. Bytes 6 through 15 are reserved and should be set to zero.
The data transferred to the EEPROM must be in the format specified in Table 5-6 of this data sheet. Maximum data transfer size
is 255 bytes.
The data transfer length is determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTransfer-
Length) of the CBW. The type/direction of the command will be determined by the direction bit specified in byte 12, bit 7 (bmCBW-
Flags) of the CBW.
Table 5-1. Command Block Wrapper
03
47
811 (08h-0Bh)
12 (0Ch)
13 (0Dh)
14 (0Eh)
15-30 (0Fh1Eh)
7 6 54321
DCBWSignature
dCBWTag
dCBWDataTransferLength
bwCBWFLAGS
Dir Obsolete
Reserved (0)
Reserved (0)
bCBWLUN
Reserved (0)
bCBWCBLength
CBWCB (CfgCB or MfgCB)
0
Table 5-2. Example CfgCB
CfgCB Byte Descriptions
0 bVSCBSignature (set in configuration bytes)
Bits
76543210
00100100
Document #: 38-08011 Rev. *B
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