PDF DAC712P Data sheet ( Hoja de datos )

Número de pieza	DAC712P
Descripción	16-BIT DIGITAL-TO-ANALOG CONVERTER With 16-Bit Bus Interface
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ® DAC712 DAC712 DAC712 16-BIT DIGITAL-TO-ANALOG CONVERTER With 16-Bit Bus Interface FEATURES q HIGH-SPEED 16-BIT PARALLEL DOUBLE- BUFFERED INTERFACE q VOLTAGE OUTPUT: ±10V q 13-, 14-, AND 15-BIT LINEARITY GRADES q 16-BIT MONOTONIC OVER TEMPERATURE (L GRADE) q POWER DISSIPATION: 600mW max q GAIN AND OFFSET ADJUST: Convenient for Auto-Cal D/A Converters q 28-LEAD DIP AND SOIC PACKAGES DB0 DB15 DESCRIPTION DAC712 is a complete 16-bit resolution D/A converter with 16 bits of monotonicity over temperature. DAC712 has a precision +10V temperature compen- sated voltage reference, ±10V output amplifier and 16-bit port bus interface. The digital interface is fast, 60ns minimum write pulse width, is double-buffered and has a CLEAR function that resets the analog output to bipolar zero. GAIN and OFFSET adjustment inputs are arranged so that they can be easily trimmed by external D/A converters as well as by potentiometers. DAC712 is available in two linearity error perfor- mance grades: ±4LSB and ±2LSB and three differen- tial linearity grades: ±4LSB, ±2LSB, and ±1LSB. The DAC712 is specified at power supply voltages of ±12V and ±15V. DAC712 is packaged in a 28-pin 0.3" wide plastic DIP and in a 28-lead wide-body plastic SOIC. The DAC712P, U, PB, UB, are specified over the –40°C to +85°C temperature range and the DAC712PK, UK, PL, UL are specified over the 0°C to +70°C range. A1 A0 WR CLR Reference Circuit Input Latch 16 D/A Latch 16 16-Bit D/A Converter VOUT Gain Adjust VREF OUT +10V Bipolar Offset Adjust International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1994 Burr-Brown Corporation PDS-1164G Printed in U.S.A. May, 1998 1 page PIN CONFIGURATION DCOM 1 ACOM 2 VOUT Offset Adjust 3 4 VREF OUT Gain Adjust 5 6 +VCC –VCC CLR 7 8 9 WR 10 A1 11 A0 12 D15 MSB 13 D14 14 DAC712 28 LSB D0 27 D1 26 D2 25 D3 24 D4 23 D5 22 D6 21 D7 20 D8 19 D9 18 D10 17 D11 16 D12 15 D13 PIN DESCRIPTIONS PIN LABEL DESCRIPTION 1 DCOM Power Supply return for digital currents. 2 ACOM Analog Supply Return. 3 VOUT ±10V D/A Output. 4 Off Adj Offset Adjust (Bipolar). 5 VREF OUT Voltage Reference Output. 6 Gain Adj Gain Adjust. 7 +VCC +12V to +15V Supply. 8 –VCC –12V to –15V Supply. 9 CLR CLEAR. Sets D/A output to BIPOLAR ZERO (Active Low). 10 WR Write (Active Low). 11 A1 Enable for D/A latch (Active Low). 12 A0 Enable for Input latch (Active Low). 13 D15 Data Bit 15 (Most Significant Bit). 14 D14 Data Bit 14. 15 D13 Data Bit 13. 16 D12 Data Bit 12. 17 D11 Data Bit 11. 18 D10 Data Bit 10. 19 D9 Data Bit 9. 20 D8 Data Bit 8. 21 D7 Data Bit 7. 22 D6 Data Bit 6. 23 D5 Data Bit 5. 24 D4 Data Bit 4. 25 D3 Data Bit 3. 26 D2 Data Bit 2. 27 D1 Data Bit 1. 28 D0 Data Bit 0 (Least Significant Bit). The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 5 DAC712 5 Page A0 is the enable control for the DATA INPUT LATCH. A1 is the enable for the D/A LATCH. WR is used to strobe data into latches enabled by A0, and A1. Refer to the block diagram of Figure 1 and to Timing Diagram on page 3. CLR sets the INPUT DATA LATCH to all zero and the D/A LATCH to a code that gives bipolar 0V at the D/A output. SINGLE-BUFFERED OPERATION To operate the DAC712 interface as a single-buffered latch, the DATA INPUT LATCH is permanently enabled by connecting A0 to DCOM. If A1 is not used to enable the D/A, it should be connected to DCOM also. For this mode of operation, the width of WR will need to be at least 80ns minimum to pass data through the DATA INPUT LATCH and into the D/A LATCH. TRANSPARENT INTERFACE The digital interface of the DAC712 can be made transpar- ent by asserting AO, A1, and WR LOW, and asserting CLR HIGH. Internal +10V Reference VREF OUT 5 170Ω 15kΩ ≈ +2.5V 250Ω R1 500Ω Gain Adjust 6 Bipolar Offset Adjust 4 R2 500Ω 120Ω 180Ω 9.75kΩ 10kΩ R3 27kΩ R4 10kΩ IDAC 0-2mA 2 ACOM FIGURE 6. Manual Offset and Gain Adjust Circuits. 3 ±10V VOUT For no external adjustments, pins 4 and 6 are not connected. External resistors R1 - R4 are standard ±1% values. Range of adjustment at least ±0.3% FSR. ® 11 DAC712 11 Page

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