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PDF DAC600 Data sheet ( Hoja de datos )
| Número de pieza | DAC600 | |
| Descripción | 12-Bit 256MHz Monolithic DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DAC600 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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® DAC600
DEMO BOARD
AVAILABLE
12-Bit 256MHz Monolithic
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 12-BIT RESOLUTION
q 256MHz UPDATE RATE
q –73dB HARMONIC DISTORTION AT 10MHz
q LASER TRIMMED ACCURACY: 1/2LSB
q –5.2V SINGLE POWER SUPPLY
q EDGE-TRIGGERED LATCH
q LOW GLITCH: 5.6pVs
q WIDEBAND MULTIPLYING REFERENCE
INPUT
q 50Ω OUTPUT IMPEDANCE
DESCRIPTION
The DAC600 is a monolithic, high performance digi-
tal-to-analog converter for high frequency waveform
generation. The internal segmentation and latching
minimize output glitch energy and maximizes AC
performance. Resistor laser trimming provides for
excellent DC linearity.
The ECL compatibility provides for low digital noise
at high update rates. The complementary 50Ω outputs
and low output capacitance simplifies transmission
line design and filtering at the output.
The DAC600 combines precision thin film and bipolar
technology to create a high performance, cost effec-
tive solution for modern waveform synthesis.
APPLICATIONS
q DIRECT DIGITAL SYNTHESIS
q ARBITRARY WAVEFORM GENERATION
q HIGH RESOLUTION GRAPHICS
q COMMUNICATIONS LOCAL
OSCILLATORS
Spread Spectrum/Frequency Hopping
Base Stations
Digitally Tuned Receivers
CLK CLK
12-Bit
ECL Lines
–20mA
Control
Amplifier
50Ω
50Ω
VREF
ROFFSET
VOUT
VOUT
LGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1992 Burr-Brown Corporation
PDS-1153E
Printed in U.S.A. November, 1996
1 page  
TYPICAL PERFORMANCE CURVES
At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT. Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK/2, unless
otherwise noted.
0.024
DIFFERENTIAL NON-LINEARITY (+25°C)
0.024
DIFFERENTIAL NON-LINEARITY (+85°C)
0.012
0.012
0.0 0.0
–0.012
–0.012
–0.024
0
1000
2000
Code
3000
4000
–0.024
0
1000
2000
Code
3000
4000
0.024
DIFFERENTIAL NON-LINEARITY (–40°C)
0.012
0.0
–0.012
–0.024
0
1000
2000
Code
3000
4000
0.048
0.024
0.0
–0.024
–0.048
0
INTEGRAL NON-LINEARITY (+85°C)
1000
2000
Code
3000
4000
0.048
0.024
0.0
–0.024
–0.048
0
INTEGRAL NON-LINEARITY (+25°C)
1000
2000
Code
3000
4000
0.048
0.024
0.0
–0.024
–0.048
0
INTEGRAL NON-LINEARITY (–40°C)
1000
2000
Code
3000
4000
®
5 DAC600
5 Page 
CLK
Data
Clock 0
Data 0
Clock 1
tPWL
tPWH
Clock 2
Data 1
Data 2
VOUT
tP
tPLSB
tPMSB
tSU tH
SYMBOL
tP
tSU
tH
tPWL
tPWH
tPMSB
tPLSB
DESCRIPTION
Propagation delay. 50% of CLK to 50% of VOUT.
Setup time DATA must remain stable before CLK.
Hold time DATA must remain stable after CLK.
CLK pulse width low (50% to 50%).
CLK pulse width high (50% to 50%).
Propagation delay, MSBs, transparent mode only.
Propagation delay, LSBs, transparent mode only.
VOUT 1
MIN
1.5
1.9
1.95
1.95
TYP MAX UNITS
2 ns
1.0 ps
1.7 ns
ns
ns
2.1 ns
1.5 ns
FIGURE 5. Timing Diagram.
analog ground plane. For speeds of up to 256MHz, series
termination with 47Ω resistors will be adequate (Figure 6).
This termination technique will greatly lessen the issue of
termination currents coupling into the analog ground plane.
This is shown in the typical DAC600 connection diagram
(Figure 7.)
ALTCOMPB and ALTCOMPC should be bypassed with
0.1µF capacitors connected to VEEA. When not used in the
multiplying mode LBIAS should be bypassed with a 0.4µF
capacitor connected to VEEA. The heat spreader (pins 26 and
44) should be bypassed with a 0.1µF capacitor.
MAXIMIZING PERFORMANCE
ECL Drive Gates
Recommended
Pull Down Resistor
47Ω DAC600
Bit
Input
–5.2V
FIGURE 6. Series Bit Termination.
LAYOUT AND POWER SUPPLIES
A multilayer PC board with a solid ground and power planes
is recommended. All of the ground pins (both analog and
digital) should be connected directly to the analog ground
plane at the DAC600.
Wide busses for the power paths are recommended as good
general practice. External bypassing is recommended. A
10µF ceramic capacitor in parallel with a 0.01µF chip
capacitor will be sufficient in most applications.
In addition to optimizing the layout and ground of the
DAC600, there are other important issues to consider when
optimizing the performance of this DAC in various AC
applications.
The DAC600 includes an internal 50Ω output impedance to
simplify output interfacing to a 50Ω load. Because some
loads may be a complex impedance, care must be taken to
match the output impedance with the load. Mismatching of
impedances can cause reflections which will affect the
measured AC performance parameters such as settling time,
harmonic distortion, rise/fall times, etc. Often complex im-
pedances can be matched by placing a variable 3 to 10pF
capacitor at the output of the DAC to ground. Also, probing
the output of the DAC can present a complex impedance.
The typical performance curves of Spurious Free Dynamic
Range vs various combinations of clock rate and/or input
frequency should give a general idea of the spectral perfor-
mance of the DAC under system specific clock and output
frequencies. For variable frequency DDS and ARB applica-
tions, having a programmable frequency bandpass (smart)
filter at the output of the DAC can greatly improve system
®
11 DAC600
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DAC600.PDF ] | |
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