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What is DAC811?

This electronic component, produced by the manufacturer "Burr-Brown Corporation", performs the same function as "Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER".


DAC811 Datasheet PDF - Burr-Brown Corporation

Part Number DAC811
Description Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER
Manufacturers Burr-Brown Corporation 
Logo Burr-Brown Corporation Logo 


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® DAC811
For most current data sheet and other product
information, visit www.burr-brown.com
Microprocessor-Compatible
12-BIT DIGITAL-TO-ANALOG CONVERTER
FEATURES
q SINGLE INTEGRATED CIRCUIT CHIP
q MICROCOMPUTER INTERFACE:
DOUBLE-BUFFERED LATCH
q VOLTAGE OUTPUT: ±10V, ±5V, +10V
q MONOTONICITY GUARANTEED OVER
TEMPERATURE
q ±1/2LSB MAXIMUM NONLINEARITY OVER
TEMPERATURE
q GUARANTEED SPECIFICATIONS AT ±12V
AND ±15V SUPPLIES
q TTL/5V CMOS-COMPATIBLE LOGIC
INPUTS
DESCRIPTION
The DAC811 is a complete, single-chip integrated-
circuit, microprocessor-compatible, 12-bit digital-to-
analog converter. The chip combines a precision volt-
age reference, microcomputer interface logic, and
double-buffered latch, in a 12-bit D/A converter with
a voltage output amplifier. Fast current switches and a
laser-trimmed thin-film resistor network provide a
highly accurate and fast D/A converter.
Microcomputer interfacing is facilitated by a double-
buffered latch. The input latch is divided into three
4-bit nibbles to permit interfacing to 4-, 8-, 12-, or
16-bit buses and to handle right-or left-justified data.
The 12-bit data in the input latches is transferred to the
D/A latch to hold the output value.
Input gating logic is designed so that loading the last
nibble or byte of data can be accomplished simulta-
neously with the transfer of data (previously stored in
adjacent latches) from adjacent input latches to the
D/A latch. This feature avoids spurious analog output
values while using an interface technique that saves
computer instructions.
The DAC811 is laser trimmed at the wafer level and
is specified to ±1/4LSB maximum linearity error (B,
K, and S grades) at 25°C and ±1/2LSB maximum over
the temperature range. All grades are guaranteed mono-
tonic over the specification temperature range.
The DAC811 is available in six performance grades
and three package types. DAC811J and K are speci-
fied over the temperature ranges of 0°C to +70°C;
DAC811A and B are specified over –25°C to +85°C;
DAC811R and S are specified over –55°C to +125°C.
DAC811J and K are packaged in a reliable 28-pin
plastic DIP or plastic SOIC package, while DAC811A,
B, R and S are available in a 28-pin 0.6" wide dual-
inline hermetically sealed ceramic side-brazed pack-
age (H package).
4 MSBs
4 LSBs
Input Latch Input Latch Input Latch
D/A Latch
12-Bit D/A Converter
Voltage Reference
RBPO
BPO
SJ
RF 10V
RF
VOUT
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1983 Burr-Brown Corporation
PDS1-503K
DAC811Printed in U.S.A. January, 2000
®

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DAC811 equivalent
1
0.1
0.01
0.001
–VCC
VDD
+VCC
0.0001
10 100 1k 10k 100k 1M
Frequency (Hz)
FIGURE 1. Power Supply Rejection vs Power Supply Ripple
Frequency.
OPERATION
DAC811 is a complete single IC chip 12-bit D/A converter.
The chip contains a 12-bit D/A converter, voltage reference,
output amplifier, and microcomputer-compatible input logic
as shown in Figure 2.
INTERFACE LOGIC
Input latches A, B, and C hold data temporarily while a
complete 12-bit word is assembled before loading into the
D/A register. This double-buffered organization prevents the
generation of spurious analog output values. Each register is
independently addressable.
These input latches are controlled by NA, NB, NC, and WR.
NA, NB, and NC are internally NORed with WR so that the
input latches transmit data when both NA (or NB, NC ) and
WR are at logic 0. When either NA, (NB, NC) or WR go to
logic 1, the input data is latched into the input registers and
held until both NA (or NB, NC ) and WR go to logic 0.
The D/A latch is controlled by LDAC and WR. LDAC and
WR are internally NORed so that the latches transmit data to
the D/A switches when both LDAC and WR are at logic 0.
When either LDAC or WR are at logic 1, the data is latched
in the D/A latch and held until LDAC and WR go to logic 0.
All latches are level-triggered. Data present when the con-
trol signals are logic 0 will enter the latch. When any one of
the control signals returns to logic 1, the data is latched.
Table II is a truth table for all latches.
WR NA
1X
00
01
01
01
00
NB
X
1
0
1
1
0
“X” = Don’t care.
NC LDAC OPERATION
X X No operation
1 1 Enables input latch 4MSBs
1 1 Enables input latch 4 middle bits
0 1 Enables input latch 4LSBs
1 0 Loads D/A latch from input latches
0 0 Makes all latches transparent
TABLE II. DAC813 Interface Logic Truth Table.
GAIN AND OFFSET ADJUSTMENTS
Figures 3 and 4 illustrate the relationship of offset and gain
adjustments to unipolar and bipolar D/A converter output.
OFFSET ADJUSTMENT
For unipolar (USB) configurations, apply the digital input
code that should produce zero voltage output, and adjust the
offset potentiometer for zero output. For bipolar (BOB,
BTC) configurations, apply the digital input code that should
produce the maximum negative output voltage and adjust
the offset potentiometer for minus full scale voltage. Ex-
ample: If the full scale range is connected for 20V, the
maximum negative output voltage is –10V. See Table III for
corresponding codes.
WR 2
NA 4
NB 5
NC 6
LDAC 3
MSB D11
78
D8
9 10
4-Bit Latch, A
Ref Out 28
Reference
FIGURE 2. DAC811 Block Diagram.
D7 D4
11 12 13 14
4-Bit Latch, B
D3 D0 LSB
19 18 17 16
4-Bit Latch, C
12-Bit D/A Latch
12-Bit D/A Converter
RBPO
RF
RF
27 BPO
26 SJ
25
10V
Range
24 VOUT
23 ACOM
®
5 DAC811


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