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PDF AM79C989 Data sheet ( Hoja de datos )
| Número de pieza | AM79C989 | |
| Descripción | Quad Ethernet Switching Transceiver (QuEST) | |
| Fabricantes | Advanced Micro Devices | |
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PRELIMINARY
Am79C989
Quad Ethernet Switching Transceiver (QuEST™)
DISTINCTIVE CHARACTERISTICS
s Four independent 10BASE-T transceivers
compliant with the IEEE 802.3 standard
s Four digital Manchester Encode/Decode
(MENDEC) units
s On-chip filtering enables FCC EMI compliance
without external filters or common mode
chokes
s Automatic polarity Correction and Detection on
10BASE-T receivers
s Optional Attachment Unit Interface (AUI) for
non-10BASE-T transceivers
s 10BASE-T Extended Distance option
accommodate lines longer than 100 meters
s Quad AMD Switching Interface (QuASI™)
interface reduces overall pin count
s Half-Duplex and Full-Duplex operation
s Auto-Negotiation compliant with IEEE 802.3u
Standard
s Standard MII management interface and
protocol
s Status Change Interrupt output pin for fast
response time to changed conditions
s 44-pin PLCC CMOS device
s 5 V supply with 3.3 V system interface
compatibility
GENERAL DESCRIPTION
The Am79C989 Quad Ethernet Switching Transceiver
(QuEST™) is a four-port physical layer (PHY) device
that provides all of the analog functions needed for a
10BASE-T switch, including four independent
Manchester Encode/Decode units (MENDECs) and
four independent 10BASE-T transceivers. If the AUI
port is used for a 10BASE-2, 10BASE-5, or
10BASE-FL transceiver, one of the four 10BASE-T
ports is disabled.
The QuEST device is designed for 10 Mbps Ethernet
switching hubs, port switching repeater hubs, routers,
bridges, and servers that require data encoding and
clock recovery on a per port basis and are limited by pin
constraints. Clock recovery is performed as part of the
MENDEC function. The QuEST device supports every
physical layer function of a full-featured switch, includ-
ing full-duplex operation with Auto-Negotiation and the
ability to use various media types.
A unique feature of the QuEST device is the Quad AMD
Switching Interface (QuASI) which multiplexes the data
for all four channels into one set of pins. This minimizes
the pin count and size of the QuEST device and sub-
stantially reduces overall system cost.
The QuEST device provides a 2-pin Media Indepen-
dent Interface (MII) Management Interface which sup-
ports the protocols specified in the IEEE 802.3u
standard. Controlled by the switch system, this inter-
face allows the QuEST device to be polled for status in-
formation and allows operating parameters of the
QuEST device, such as extended distance operation,
to be altered.
The Am79C989 device provides an Interrupt pin to in-
dicate changes in the internal status of the device. The
interrupt function reduces CPU polling of status regis-
ters and allows fast response time to changes in phys-
ical layer conditions.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 21173 Rev: B Amendment/+2
Issue Date: April 1997
1 page  
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Description
Local Area Network Controller for Ethernet (LANCE)
Serial Interface Adapter (SIA)
IEEE 802.3/Ethernet/Cheapernet Transceiver
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Twisted Pair Ethernet Transceiver (TPEX)
Twisted Pair Ethernet Transceiver Plus (TPEX+)
Quad Fast Ethernet Transceiver (QFEX™) for 100BASE-X
Quad Fast Ethernet Transceiver for 100BASE-X Repeater (QFEXr™)
Integrated Multiport Repeater Plus (IMR+™)
basic Integrated Multiport Repeater (bIMR™)
Integrated Multiport Repeater 2 (IMR2™)
enhanced Integrated Multiport Repeater (eIMR™)
enhanced Integrated Multiport Repeater Plus (eIMR+™)
Hardware Implemented Management Information Base (HIMIB™)
Quad Integrated Ethernet Transceiver (QuIET™)
Integrated Local Area Communications Controller (ILACC™)
Media Access Controller for Ethernet (MACE™)
PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)
PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support)
PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA
PCnet™-32 Single-Chip 32-Bit Ethernet Controller
PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)
PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)
PCnet™-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C989
5
5 Page 
PRELIMINARY
RXD3±
10BASE-T Receive Data Port 3
Input
RXD3± are the 10BASE-T differential data receivers for
port 3.
AUI Signal Pins
DO±
AUI Data Out
Output
When Port 0 is configured for AUI, DO± are the AUI dif-
ferential data out drivers. Data is transmitted with
Manchester encoded signaling compliant with IEEE
802.3 standards.
DI±
AUI Data In
Input
When Port 0 is configured for AUI (Control Register
Reg 18 bit 2), DI± are the AUI differential data in receiv-
ers. Data is indicated by Manchester encoded signal-
ing compliant with IEEE 802.3 standards.
PCI/CI+
Pseudo-AUI Collision, AUI Collision Int (-)
Input/Input
When Interrupt Enable is true (Control Register Reg 18
bit 5) and port 0 is configured for AUI (Control Register
Reg 18 bit 2), this pin is configured as PCI. PCI is a sin-
gle-ended pseudo-AUI collision in signal. Collision is in-
dicated by a 10 MHz pattern.
When Interrupt Enable is false (Control Register Reg
18 bit 5) and port 0 is configured for AUI (Control Reg-
ister Reg 18 bit 2), this pin is configured as CI+. CI± are
the AUI differential collision in signals. Collision is indi-
cated by a 10 MHz pattern compliant with IEEE 802.3
standards.
QINT/CI-
QuEST Interrupt, AUI Collision Int (-)
Output/Input
When Interrupt Enable is true (Control Register Reg.
18 bit 5), this pin is configured as QINT. QINT is an ac-
tive-low signal which indicates that one of the following
conditions has occurred: Link Status Change, Duplex
Mode Change, Auto-Negotiation Change, MAU Error.
Interrupt status flags and enables for individual condi-
tions are reported in the Interrupt Status and Enable
Register (Reg 16).
When Interrupt Enable is false (Control Register Reg
18 bit 5) and port 0 is configured for AUI (Control Reg-
ister Reg 18 bit 2), this pin is configured as CI-. CI± are
the AUI differential collision in signals. Collision is indi-
cated by a 10-MHz pattern compliant with IEEE 802.3
standards.
QuASI Interface
QTX_EN
Multiplexed Transmit Enable
Input
QTX_EN indicates to QuEST that valid transmit data is
on QTX_DATA. QTX_EN for all 4 ports is time-division
multiplexed onto this signal and is sampled with re-
spect to SCLK. The channel’s slot is synchronized to
the rising edge of QRST/STRB.
QTX_DATA
Multiplexed Transmit Data
Input
QTX_DATA indicates serial NRZ transmit data.
QTX_DATA for all 4 ports is time-division multiplexed
onto this signal and is sampled with respect to SCLK.
The channel’s slot is synchronized to the rising edge of
QRST/STRB.
QRX_CRS
Multiplexed Receive Carrier Sense
Output
QRX_CRS indicates receive or transmit activity on the
network. QRX_CRS for all 4 ports is time-division mul-
tiplexed onto this signal and is sampled with respect to
SCLK. The channel’s slot is synchronized to the rising
edge of QRST/STRB.
QRX_VALID
Multiplexed Receive Data Valid
Output
QRX_VALID indicates that valid receive data is on
QRX_DATA. QRX_VALID for all 4 ports is time-division
multiplexed onto this signal and is sampled with re-
spect to SCLK. The channel’s slot is synchronized to
the rising edge of QRST/STRB. At the rising edge of re-
set, QRX_VALID is sampled to determine PHYAD 3.
QRX_DATA
Multiplexed Receive Data
Output
QRX_DATA indicates serial NRZ receive data.
QRX_DATA for all 4 ports is time-division multiplexed
onto this signal and is sampled with respect to SCLK.
The channel’s slot is synchronized to the rising edge of
QRST/STRB. At the rising edge of reset, QRX_DATA is
sampled to determine PHYAD 4.
QCLSN
Multiplexed Collision
Output
QCLSN indicates a collision condition on the network.
QCLSN for all 4 ports is time-division multiplexed onto
this signal and is sampled with respect to SCLK. The
channel’s slot is synchronized to the rising edge of
QRST/STRB. At the rising edge of reset, QCLSN is
sampled to determine PHYAD 2.
Am79C989
11
11 Page | ||
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| PDF Descargar | [ Datasheet AM79C989.PDF ] | |
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