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PDF AM79C32A Data sheet ( Hoja de datos )

Número de pieza AM79C32A
Descripción Digital Subscriber Controller (DSC) Circuit
Fabricantes Advanced Micro Devices 
Logotipo Advanced Micro Devices Logotipo



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FINAL
Am79C30A/32A
Digital Subscriber Controller™ (DSC™) Circuit
DISTINCTIVE CHARACTERISTICS
s Combines CCITT I.430 S/T-Interface Transceiver,
D-Channel LAPD Processor, Audio
s Processor (DSC device only), and IOM-2
Interface in a single chip
s Special operating modes allow realization of
CCITT I.430 power-compliant terminal
equipment
s S- or T-Interface Transceiver
— Level 1 Physical Layer Controller
— Supports point-to-point, short and extended
passive bus configurations
— Provides multiframe support
s Certified protocol software support available
s CMOS technology, TTL compatible
s D-channel processing capability
— Flag generation/detection
— CRC generation/checking
— Zero insertion/deletion
— Four 2-byte address detectors
— 32-byte receive and 16-byte transmit FIFOs
BLOCK DIAGRAM
CAP1
CAP2
SBP/IOM-2 Interface
SBIN
SCLK BCL/CH2STRB*
SBIOUT SFS
HSW
AINA
AREF
AINB
EAR1
EAR2
LS1
LS2
XTAL1
XTAL2
MCLK
CS
WR
RD
Main Audio
Processor (MAP)
(Am79C30A
Only)
Ba
Oscillator
(OSC)
Peripheral Port
(PP)
Bd Be Bf
B-channel Multiplexer
(MUX)
B1
B2
Bb Bc
Microprocessor Interface
(MUX)
S/T Line
Interface Unit
(LIU)
D
Channel
LOUT1
LOUT2
LIN1
LIN2
D-Channel Data
Link Controller
(DLC)
D
Channel
RESET
D7 D6 D5 D4 D3 D2 D1 D0 INT A2 A1 A0
Microprocessor Interface
09893H-1
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 09893 Rev: H Amendment/0
Issue Date: December 1998

1 page




AM79C32A pdf
ORDERING INFORMATION
Standard Products
AMD® standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
AM79C30A/32A
JC
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
V = 44-Pin Thin Plastic Quad Flat Pack (PQT044)
SPEED OPTION
Not Applicable
DEVICE NAME/DESCRIPTION
Am79C30A/32A
Digital Subscriber Controller (DSC) device
ISDN Data Controller (IDC) device
Valid Combinations
AM79C30A
JC, VC
AM79C32A
JC, VC
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Reference Appendix C, Figures 1 & 2, for specific mechanical dimensions of the two packages.
Am79C30A/32A Data Sheet
5

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AM79C32A arduino
Bc buffers must be accessed within 122.4 µs. This is to
prevent erroneous data transfers. Only one interrupt is
used to signal accessibility for both B channels of the S
Interface. Since the data transfer must occur synchro-
nously to the S Interface, any data access to either Bb
or Bc or both must be made within the122.4 µs limit.
Note that even though only a single interrupt is issued,
either or both S-Interface B channels must be serviced.
IR bits 2, 3, 5, 6, and 7, if set, indicate that a bit has
been set in the associated status or error register. All of
the interrupts generated by the Am79C30A/32A can be
individually disabled. In the case of IR bit 7, the inter-
rupt can also be masked by setting PPIER bit 7 to 0.
DMR1, DMR2, DMR3, LMR2, MCR4, and MF control
the mask conditions that affect the INT pin. The INT pin
is activated only by interrupts that are not disabled. The
Interrupt Register reflects the status of enabled inter-
rupts. The INT pin can be disabled by setting INIT Reg-
ister bit 2 to a logical 1.
The Am79C30A/32A has facilities that allow the micro-
processor to read the status registers (status update is
inhibited during status read) or the IR at any time dur-
ing functional operation.
Am79C30A/32A Data Sheet
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