|
|
PDF AM29LV64MU120RWHI Data sheet ( Hoja de datos )
| Número de pieza | AM29LV64MU120RWHI | |
| Descripción | 64 Megabit (4 M x 16-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AM29LV64MU120RWHI (archivo pdf) en la parte inferior de esta página. Total 58 Páginas | ||
|
No Preview Available !
Am29LV640MU
Data Sheet
-XO\
7KH IROORZLQJ GRFXPHQW VSHFLILHV 6SDQVLRQ PHPRU\ SURGXFWV WKDW DUH QRZ RIIHUHG E\ ERWK $GYDQFHG
0LFUR 'HYLFHV DQG )XMLWVX $OWKRXJK WKH GRFXPHQW LV PDUNHG ZLWK WKH QDPH RI WKH FRPSDQ\ WKDW RULJ
LQDOO\ GHYHORSHG WKH VSHFLILFDWLRQ WKHVH SURGXFWV ZLOO EH RIIHUHG WR FXVWRPHUV RI ERWK $0' DQG
)XMLWVX
Continuity of Specifications
7KHUH LV QR FKDQJH WR WKLV GDWDVKHHW DV D UHVXOW RI RIIHULQJ WKH GHYLFH DV D 6SDQVLRQ SURGXFW $Q\
FKDQJHV WKDW KDYH EHHQ PDGH DUH WKH UHVXOW RI QRUPDO GDWDVKHHW LPSURYHPHQW DQG DUH QRWHG LQ WKH
GRFXPHQW UHYLVLRQ VXPPDU\ ZKHUH VXSSRUWHG )XWXUH URXWLQH UHYLVLRQV ZLOO RFFXU ZKHQ DSSURSULDWH
DQG FKDQJHV ZLOO EH QRWHG LQ D UHYLVLRQ VXPPDU\
Continuity of Ordering Part Numbers
$0' DQG )XMLWVX FRQWLQXH WR VXSSRUW H[LVWLQJ SDUW QXPEHUV EHJLQQLQJ ZLWK $P DQG 0%0 7R RUGHU
WKHVH SURGXFWV SOHDVH XVH RQO\ WKH 2UGHULQJ 3DUW 1XPEHUV OLVWHG LQ WKLV GRFXPHQW
For More Information
3OHDVH FRQWDFW \RXU ORFDO $0' RU )XMLWVX VDOHV RIILFH IRU DGGLWLRQDO LQIRUPDWLRQ DERXW 6SDQVLRQ
PHPRU\ VROXWLRQV
QiyvphvÃIir
Ã!$" à Srvv Ã8 6rqr à à DrÃ9hr ÃErà !Ã!"
1 page  
ADVANCE INFORMATION
TABLE OF CONTENTS
MirrorBit 64 Mbit Device Family . . . . . . . . . . . . . . 3
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Special Package Handling Instructions .................................... 7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .....................................................10
VersatileIO (VIO) Control ..................................................... 10
Requirements for Reading Array Data ................................... 10
Page Mode Read .................................................................... 11
Writing Commands/Command Sequences ............................ 11
Write Buffer ............................................................................. 11
Accelerated Program Operation ............................................. 11
Autoselect Functions .............................................................. 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Sector Address Table ........................................................13
Autoselect Mode..................................................................... 15
Table 3. Autoselect Codes, (High Voltage Method) .......................15
Sector Group Protection and Unprotection ............................. 16
Table 4. Sector Group Protection/Unprotection Address Table .....16
Temporary Sector Group Unprotect ....................................... 17
Figure 1. Temporary Sector Group Unprotect Operation................ 17
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18
SecSi (Secured Silicon) Sector Flash Memory Region .......... 19
Table 5. SecSi Sector Contents ......................................................19
Figure 3. SecSi Sector Protect Verify.............................................. 20
Hardware Data Protection ...................................................... 20
Low VCC Write Inhibit ............................................................ 20
Write Pulse “Glitch” Protection ............................................... 20
Logical Inhibit .......................................................................... 20
Power-Up Write Inhibit ............................................................ 20
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 6. CFI Query Identification String .............................. 21
Table 7. System Interface String......................................................21
Table 8. Device Geometry Definition................................... 22
Table 9. Primary Vendor-Specific Extended Query............. 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................ 24
Reset Command ..................................................................... 24
Autoselect Command Sequence ............................................ 24
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25
Word Program Command Sequence ..................................... 25
Unlock Bypass Command Sequence ..................................... 25
Write Buffer Programming ...................................................... 25
Accelerated Program .............................................................. 26
Figure 4. Write Buffer Programming Operation............................... 27
Figure 5. Program Operation .......................................................... 28
Program Suspend/Program Resume Command Sequence ... 28
Figure 6. Program Suspend/Program Resume............................... 29
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
Figure 7. Erase Operation.............................................................. 30
Command Definitions ............................................................. 31
Table 10. Command Definitions...................................................... 31
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling ................................................................. 32
Figure 8. Data# Polling Algorithm .................................................. 32
RY/BY#: Ready/Busy#............................................................ 33
DQ6: Toggle Bit I .................................................................... 33
Figure 9. Toggle Bit Algorithm........................................................ 34
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ............................................... 34
DQ5: Exceeded Timing Limits ................................................ 35
DQ3: Sector Erase Timer ....................................................... 35
DQ1: Write-to-Buffer Abort ..................................................... 35
Table 11. Write Operation Status ................................................... 35
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 36
Figure 10. Maximum Negative Overshoot Waveform ................... 36
Figure 11. Maximum Positive Overshoot Waveform..................... 36
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. Test Setup.................................................................... 38
Table 12. Test Specifications ......................................................... 38
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
Figure 13. Input Waveforms and
Measurement Levels...................................................................... 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ........................................................... 39
Figure 14. Read Operation Timings ............................................... 39
Figure 15. Page Read Timings ...................................................... 40
Hardware Reset (RESET#) .................................................... 41
Figure 16. Reset Timings............................................................... 41
Erase and Program Operations .............................................. 42
Figure 17. Program Operation Timings.......................................... 43
Figure 18. Accelerated Program Timing Diagram.......................... 43
Figure 19. Chip/Sector Erase Operation Timings .......................... 44
Figure 20. Data# Polling Timings
(During Embedded Algorithms)...................................................... 45
Figure 21. Toggle Bit Timings
(During Embedded Algorithms)...................................................... 46
Figure 22. DQ2 vs. DQ6................................................................. 46
Temporary Sector Unprotect .................................................. 47
Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 47
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 48
Alternate CE# Controlled Erase and Program Operations ..... 49
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 50
Erase And Programming Performance. . . . . . . . 51
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 51
TSOP Pin and FIne-pitch BGA Package
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 53
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
13 x 11 mm Package .............................................................. 53
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
12 x 11 mm Package .............................................................. 54
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
4
Am29LV640MU
June 12, 2003
5 Page 
ADVANCE INFORMATION
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Operation
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
Sector Group Protect (Note 2)
Sector Group Unprotect
(Note 2)
Temporary Sector Group
Unprotect
CE# OE# WE# RESET#
L LH
H
L HL
H
L HL
H
VCC ±
0.3 V
X
X
VCC ±
0.3 V
L HH
H
X XX
L
L HL
VID
L HL
VID
X XX
VID
ACC
X
X
VHH
H
X
X
X
X
X
Addresses
(Note 2)
AIN
AIN
AIN
X
X
X
SA, A6=L, A3=L,
A2=L, A1=H, A0=L
SA, A6=H, A3=L,
A2=L, A1=H, A0=L
AIN
DQ0–
DQ15
DOUT
(Note 3)
(Note 3)
High-Z
High-Z
High-Z
(Note 3)
(Note 3)
(Note 3)
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIO (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. See “Ordering Informa-
tion” on page 9 for VIO options on this device.
For example, a VI/O of 1.65–3.6 volts allows for I/O at
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 13 for the timing diagram.
10
Am29LV640MU
June 12, 2003
11 Page | ||
| Páginas | Total 58 Páginas | |
| PDF Descargar | [ Datasheet AM29LV64MU120RWHI.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AM29LV64MU120RWHI | 64 Megabit (4 M x 16-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with | Advanced Micro Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |