AND8079 Datasheet PDF - ON Semiconductor
Part Number | AND8079 | |
Description | A Low Cost DDR Memory Power Supply Using the NCP1571 Synchronous Buck Converter and a LM358 Based Linear Voltage Regulator | |
Manufacturers | ON Semiconductor | |
Logo | ||
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A Low Cost DDR Memory
Power Supply Using the
NCP1571 Synchronous Buck
Converter and a LM358
Based Linear Voltage
Regulator
Prepared by: Jim Lepkowski
Senior Application Engineer
http://onsemi.com
APPLICATION NOTE
INTRODUCTION
This application note describes a low cost power supply
circuit for a DDR (Double Data Rate) memory system. The
design is based on the NCP1570/NCP1571 low voltage
synchronous buck converter. The reference design created
to evaluate the system uses a 3.80″ by 2.15″ two layer printed
circuit board, optimized for a small solution size at an
economical cost.
DDR memories bring new challenges to the power supply
by requiring an efficient main power of 2.5 V (Vdd) and a
second voltage (Vtt) that accurately tracks one half of Vdd
(i.e. 1.25 V) that is capable of both sourcing and sinking
current. In addition, a third voltage is required (VREF) that
also tracks Vdd/2. A low voltage synchronous buck
converter is used to create an 8.0 A output at 2.5 V, while the
Vtt and VREF voltages are created using a unique operational
amplifier linear regulator circuit. The demonstration circuit
is designed for low power DDR systems such as desktop
PCs, but the circuit’s output power capability can be
increased with the selection of the external inductor and
capacitors for high power systems such as PC workstations.
DDR Memory Power Supply Requirements
Figure 1 shows a simplified schematic of the DDR
memory system. Voltage Vdd powers the memory ICs, in
addition to the buffer interface circuits. The termination
voltage Vtt is used for the pull-up resistors and must be able
to either sink or source current. For example, if all of the
driver circuits are at a logic high state (i.e. VOH = Vdd =
2.5 V), the Vtt supply will have to sink current in order to
maintain its 1.25 V. In contrast, if all of the driver circuits are
at a logic low state (i.e. VOL = Vss = 0 V), the Vtt supply will
have to source current because the termination resistors will
be effectively connected to ground.
Vdd
Transmitter
Vtt = Vdd/2
RT
RS 25
22
VREF
Receiver
Figure 1. DDR Memory Simplified Schematic
Vtt is equal to Vdd/2 instead of Vdd in order to save power.
The power dissipated in the resistors is equal to voltage
squared divided by the bus resistance, thus a termination
voltage of Vdd/2 provides a factor of four power savings.
The third voltage is used as a reference voltage to the
differential amplifier input section of the receiver ICs.
A summary of the specifications for the DDR memory
system is listed below. The transient requirements are not
defined in the industry JEDEC standards.
DDR
Voltage
Vdd
Vtt
VREF
Output
Voltage
2.5 V
Vdd/2
(^1.25 V)
Vdd/2
Tolerance
"200 mV
Vdd/2 " 3%
(1.250 V "
37.5 mV)
Vtt " 40 mV
Output Current
8.0 A
"2.0 A
(Sink and Source)
5.0 mA
© Semiconductor Components Industries, LLC, 2002
October, 2002 - Rev. 1
1
Publication Order Number:
AND8079/D
|
|
AND8079/D
Schottky Diode for Synchronous MOSFET
The efficiency of the buck converter can be improved
slightly by placing a Schottky diode (D1) in parallel with the
bottom MOSFET (Q3). The body diode of Q3 is used to
conduct current during the non-overlap time when both the
top (Q2) and bottom (Q3) MOSFETs are turned OFF. But
because the non-overlap time is only approximately 50 ns
for the NCP1571’s 200 kHz switching speed, the efficiency
savings will be only approximately 1.0%. The
demonstration board included a provision for D1; however,
the performance of the circuit was not testing with this
diode.
Experimental Results
The experimental results of the demonstration PCB are
shown in Figures 4 through 20. Figure 3 shows the test setup
used to create the current load transients for the Vtt supply
voltage. The transient current load tests for the Vdd and Vtt
supply voltages were created using a Kikusui Electronic
Load Controller. Unless noted, the standard test conditions
are as listed below:
1. Ambient Temperature = 23_C
2. Vdd Current Load (IVdd) = 8.0 A
3. Vtt Current Load (IVtt) = 1.25 A source load
4. VREF Current Load (IREF) = 2.5 mA
5. 5.0 V Input Voltage = 5.00 V
6. 12 V Input Voltage = 12.00 V
7. -12 V Input Voltage = -12.00 V
Vtt DDR Circuit
2.5 V
Vdd
Q4 - 2.0 A
+ DC Current Source
VREF
-
OUT
+
U2A
R7
+
C22
Q5
+
C23
Vtt
+ Pulsating Current Source
-
Pulse Width = 100 ms
Period = 200 ms
l1 = 0 A
l2 = 4.0 A
Rise Time = 50 ms
Fall Time = 50 ms
DC Current Source
2.0 A
Vtt Circuit
2 .0 A
Vtt
0A
Pulsating Current Source
2.0 A Current Sink Test
DC Current Source
2.0 A
Vtt Circuit
2 .0 A
Vtt
4A
Pulsating Current Source
2.0 A Current Source Test
Figure 3. Vtt Transient Load Test Setup for a 2.0 A Sink to 2.0 A Source Test
http://onsemi.com
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