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PDF HM1-6518883 Data sheet ( Hoja de datos )
| Número de pieza | HM1-6518883 | |
| Descripción | 1024 x 1 CMOS RAM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HM-6518/883
March 1997
1024 x 1 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 2 TTL Loads
• High Noise Immunity
• On-Chip Address Register
• Two-Chip Selects for Easy Array Expansion
• Three-State Output
The HM-6518/883 is a 1024 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to
achieve high performance and low power operation.
On chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.
The HM-6518/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
PACKAGE
CERDIP
TEMP. RANGE
-55oC to +125oC
PART
NUMBER
HM1-6518/883
PKG. NO.
F18.3
Pinout
HM-6518/883
(CERDIP)
TOP VIEW
S1 1
E2
A0 3
A1 4
A2 5
A3 6
A4 7
Q8
GND 9
18 VCC
17 S2
16 D
15 W
14 A9
13 A8
12 A7
11 A6
10 A5
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-85
File Number 2986.1
1 page  
HM-6518/883
TABLE 3. HM-6518/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CONDITIONS
CI VCC = Open, f = 1MHz, All Measure-
ments Referenced to Device Ground
CO VCC = Open, f = 1MHz, All Measure-
ments Referenced to Device Ground
NOTE
1
TEMPERATURE
TA = +25oC
1 TA = +25oC
MIN
-
-
MAX
6
UNITS
pF
10 pF
NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after
major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
Timing Waveforms
(8)
TAVEL
A
TEHEL (7)
E
HIGH
W
(9)
TELAX
VALID
TELEL (17)
TELEH (6)
(8)
TAVEL
TEHEL (7)
NEXT
D
Q
S1, 1
S2
PREVIOUS
DATA
TSHQZ
HIGH Z
(5)
TIME
REFERENCE
-1 0
TELQV (1)
TAVQV (2)
TSLOX
(3)
VALID OUTPUT LATCHED
(5) TSHQZ
HIGH Z
1
FIGURE 1. READ CYCLE
2
3
45
6-89
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HM1-6518883.PDF ] | |
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