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PDF HM-6617 Data sheet ( Hoja de datos )
| Número de pieza | HM-6617 | |
| Descripción | 2K x 8 CMOS PROM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HM-6617/883
March 1997
2K x 8 CMOS PROM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
• Operating Temperature Range . . . . . . -55oC to +125oC
The HM-6617/883 is a 16,384-bit fuse link CMOS PROM in
a 2K word by 8-bit/word format with “Three-State” outputs.
This PROM is available in the standard 0.600 inch wide 24
pin SBDIP, the 0.300 inch wide slim SBDIP, and the JEDEC
standard 32 pad CLCC.
The HM-6617/883 utilizes a synchronous design technique.
This includes on-chip address latches and a separate output
enable control which makes this device ideal for applications
utilizing recent generation microprocessors. This design
technique, combined with the Intersil advanced self-aligned
silicon gate CMOS process technology offers ultra-low
standby current. Low ICCSB is ideal for battery applications
or other systems with low power requirements.
The Intersil NiCr fuse link technology is utilized on this and
other Intersil CMOS PROMs. This gives the user a PROM
with permanent, stable storage characteristics over the full
industrial and military temperature voltage ranges. NiCr fuse
technology combined with the low power characteristics of
CMOS provides an excellent alternative to standard bipolar
PROMs or NMOS EPROMs.
Ordering Information
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
PACKAGE
SBDIP
SLIM SBDIP
CLCC
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
90ns
HM1-6617B/883
HM6-6617B/883
HM4-6617B/883
120ns
HM1-6617B/883
HM6-6617B/883
HM4-6617B/883
PACKAGE NO.
D24.6
D24.3
J32.A
Pinouts
HM-6617/883 (SBDIP)
TOP VIEW
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
Q0 9
Q1 10
Q2 11
GND 12
24 VCC
23 A8
22 A9
21 P
20 G
19 A10
18 E
17 Q7
16 Q6
15 Q5
14 Q4
13 Q3
HM-6617/883 (CLCC)
TOP VIEW
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
26 P
A2 9
25 G
A1 10
24 A10
A0 11
23 E
NC 12
22 Q7
Q0 13
21 Q6
14 15 16 17 18 19 20
PIN DESCRIPTION
PIN DESCRIPTION
NC No Connect
A0-A10
Address Inputs
E Chip Enable
Q Data Output
VCC
G
Power (+5V)
Output Enable
P (Note) Program Enable
NOTE: P should be hardwired to VCC
except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-250
File Number 3016.1
1 page  
HM-6617/883
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
Switching Waveforms
ADDRESSES
E
G
DATA
OUTPUT
Q0-Q7
TAVQV
1.5V
VALID
ADDRESS
1.5V
TAVEL
TELAX
1.5V
1.5V
TELEH
TEHEL
TELQV
1.5V
TGLQV
TGLQX
TELQX
TELEL
VALID
ADDRESSES
3.0V
0V
1.5V
1.5V
3.0V
1.5V
0V
TEHQZ
3.0V
0V
TGHQZ
VALID
DATA
TS
FIGURE 1. READ CYCLE
Test Circuit
DUT
CL
(NOTE)
NOTE:
TEST HEAD
CAPACITANCE
±IOH 1.5V
EQUIVALENT CIRCUIT
FIGURE 2. TEST CIRCUIT
IOL
6-254
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HM-6617.PDF ] | |
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