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PDF HV20220PJ Data sheet ( Hoja de datos )
| Número de pieza | HV20220PJ | |
| Descripción | High Voltage Analog Switch | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Supertex inc.
HV20220
Low Charge Injection,
8-Channel, High Voltage Analog Switches
Features
►►HVCMOS® technology for high performance
►►Very low quiescent power dissipation (-10µA)
►►Output on-resistance typically 22Ω
►►Low parasitic capacitances
►►DC to 50MHz small signal frequency response
►►-60dB typical output off isolation at 5.0MHz
►►CMOS logic circuitry for low power
►►Excellent noise immunity
►►On-chip shift register, latch and clear logic circuitry
►►Flexible high voltage supplies
Applications
►► Medical ultrasound imaging
►► Piezoelectric transducer drivers
General Description
This device is a low charge injection, 8-channel, high-voltage
analog switch integrated circuit (IC) intended for use in appli-
cations requiring high voltage switching controlled by low volt-
age control signals, such as ultrasound imaging and printers.
Input data is shifted into an 8-bit shift register which can then
be retained in an 8-bit latch. To reduce any possible clock
feed-through noise, Latch Enable Bar (LE) should be left high
until all bits are clocked in. Using HVCMOS® technology, this
switch combines high voltage bilateral DMOS switches and
low power CMOS logic to provide efficient control of high volt-
age analog signals.
These ICs are suitable for various combinations of high volt-
age supplies, e.g., VPP/VNN : +50V/-150V, or +100V/-100V.
Block Diagram
DIN
CLK
8-Bit
Shift
Register
DOUT
Level Output
Latches Shifters Switches
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
VDD
LE CL
VNN VPP
Doc.# DSFP-HV20220
C071613
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
Supertex inc.
www.supertex.com
1 page  
HV20220
Truth Table
D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L L L Off
H L L On
L
LL
Off
H
LL
On
L
LL
Off
H
LL
On
L
LL
Off
H
LL
On
L LL
Off
H LL
On
L LL
Off
H LL
On
L LL
Off
H LL
On
LLL
Off
HLL
On
XXXXXXXXHL
Hold Previous State
XXXXXXXXXH
All Switches Off
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. DOUT is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DN+1
DATA
IN
LE
CLOCK
DATA
OUT
VOUT
(typ) OFF
ON
DN
50%
50%
50%
tSU
SU
50%
tWLE
tSD
50%
th
tDD
50%
tOFF
90%
CLR
50%
tWCL
50%
DN-1
50%
tON
10%
Doc.# DSFP-HV20220
C071613
Supertex inc.
5 www.supertex.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HV20220PJ.PDF ] | |
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