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PDF HT49C10 Data sheet ( Hoja de datos )
| Número de pieza | HT49C10 | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT49C10
8-Bit Microcontroller
Features
· Operating voltage: 2.2V~5.2V
· Eight bidirectional I/O lines
· Six input lines
· Two external interrupt input
· 8-bit programmable timer/event counter
with PFD (programmable frequency divider)
· Watchdog timer
· On-chip crystal and RC oscillator
· 1K´14 program memory ROM
· 64´8 data memory RAM
· Real Time Clock (RTC)
· 8-bit prescaler for RTC
General Description
The HT49C10 is an 8-bit high performance single
chip microcontroller. Its single-cycle instruction
and two-stage pipeline architecture make it suit-
able for high speed applications. The device is
· Buzzer output
· Halt function and wake-up feature reduce
power consumption
· LCD driver with 19´3 or 18´4 segments
· 4-level subroutine nesting
· Bit manipulation instruction
· 14-bit table read instruction
· Up to 1ms instruction cycle with 4MHz
system clock
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· 48-pin SSOP package
also suited for multiple LCD low power applica-
tions among which are calculators, clock timers,
games, scales, leisure products, other hand held
LCD products, and battery systems in particular.
1 September 28, 1999
1 page  
HT49C10
Pad Description
Pad No.
Pad Name
I/O
Mask
Option
Description
PA0~PA7 constitute an 8-bit bidirectional input/ out-
put port with Schmitt trigger input capability. Each
45
46
47
48
1~4
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
I/O
Wake-up
Pull-high
or None
CMOS or
NMOS
bit on port can be configured as wake-up input by
mask option. PA0~PA3 can be configured as CMOS
(output) or NMOS (input/output) and with or without
pull-high resistor by mask option, PA4~PA7 always
pull-high and NMOS (input/output). Of the eight bits,
PA0~PA1 can be set as I/O pins or buzzer outputs by
mask option. PA3 can be set as an I/O pin or a PFD
output also by mask option.
5
6
7
8~10
PB0/INT0
PB1/INT1
PB2/TMR
PB3~PB5
PB0~PB5 constitute a 6-bit Schmitt trigger input
port. Each bit on port are pull-high resistor. Of the six
bits, PB0 can be set as input pin or external interrupt
I
¾
control pin (INT0) by software application. PB1 can be
set as input pin or an external interrupt control pin
(INT1) by software application. While PB2 can be set
as input pin or timer/event counter input pin also by
software application.
11 VSS
I ¾ Negative power supply, GND
12 VLCD
I ¾ LCD power supply
13~16 V1,V2,C1,C2 I
¾ Voltage pump
20
19~17
SEG18/COM3
COM2~COM0
O
1/3 or 1/4
Duty
SEG18 can be set as segment or common output driver
for LCD panel by mask option. COM2~COM0 are out-
puts for LCD panel plate.
21~38 SEG17~SEG0 O ¾ LCD driver outputs for LCD panel segments
39 OSC4
40 OSC3
O
I
¾ Real time clock oscillators
41 VDD
¾ ¾ Positive power supply
42 OSC2
43 OSC1
OSC1 and OSC2 are connected to an RC network or a
O Crystal or crystal (by mask option) for the internal system clock.
I RC In the case of RC operation, OSC2 is the output termi-
nal for 1/4 system clock.
44 RES
I ¾ Schmitt trigger reset input, active low
5 September 28, 1999
5 Page 
register 0 (MP0;01H) or the memory pointer reg-
ister 1 (MP1;03H).
0 0 H In d ir e c t A d d r e s s in g R e g is te r 0
01H M P 0
0 2 H In d ir e c t A d d r e s s in g R e g is te r 1
03H M P 1
04H B P
05H A C C
06H P C L
07H TB LP
08H TB LH
09H R TC C
0A H S TA TU S
0 B H IN T C 0
0C H
0D H TM R
0E H TM R C
0FH
10H
11H
12H P A
13H
14H P B
15H
16H
17H
18H
19H
1A H
1B H
1C H
1D H
1 E H IN T C 1
1FH
20H
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
S p e c ia l P u r p o s e
D a ta M e m o ry
:U nused
R e a d a s "0 0 "
5FH
RAM mapping
Indirect addressing register
Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] and [02H] ac-
cesses the RAM pointed to by MP0 (01H) and
HT49C10
MP1 (03H) respectively. Reading location 00H
or 02H indirectly returns the result 00H, while,
writing it leads to no operation.
The function of data movement between two in-
direct addressing registers is not supported.
The memory pointer registers, MP0 and MP1,
are both 7-bit registers used to access the RAM
by combining corresponding indirect address-
ing registers. The bit 7 of MP0 and MP1 are un-
defined and reading will return the result 1 .
Any writing operation to MP0 and MP1 will
only transfer the lower 7-bit data.
Only MP0 can be applied to data memory, while
MP1 can be applied to data memory and LCD
display memory.
Accumulator - ACC
The accumulator (ACC) is related to ALU oper-
ations. It is also mapped to location 05H of the
RAM and is capable of carrying out immediate
data operations. The data movement between
two data memory locations has to pass through
the ACC.
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic
operations and provides the following functions:
· Arithmetic operations
(ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data op-
eration but also changes the status register.
Status register - STATUS
The status register (0AH) is 8-bit wide and con-
tains a carry flag (C), an auxiliary carry flag
(AC), a zero flag (Z), an overflow flag (OV), a
power down flag (PD), and a watchdog time-out
flag (TO). It also records the status information
and controls the operation sequence.
Except for the TO and PD flags, bits in the status
register can be altered by instructions, similar to
other registers. Data written into the status reg-
11 September 28, 1999
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT49C10.PDF ] | |
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