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PDF HT23C020 Data sheet ( Hoja de datos )
| Número de pieza | HT23C020 | |
| Descripción | CMOS 256Kx 8-Bit Mask ROM | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT23C020
CMOS 256K×8-Bit Mask ROM
Features
• Operating voltage 2.7V~5.5V
• Low power consumption
– Operation: 25mA max. (VCC=5V)
10mA max. (VCC=3V)
– Standby: 30µA max. (VCC=5V)
10µA max. (VCC=3V)
• Access time:150ns max. (VCC=5V)
250ns max. (VCC=3V)
• 262144×8 bits of mask ROM
• Mask options: chip enable CE/CE/OE1/OE1,
CE1/CE1/OE2/OE2/NC and output enable
OE/OE/NC
• TTL compatible inputs and outputs
• Tristate outputs
• Fully static operation
• Package type: 32-pin DIP/SOP/PLCC
General Description
The HT23C020 is a read-only memory with
high performance CMOS storage device whose
2048K of memory is arranged into 262144
words by 8 bits.
For application flexibility, the chip enable and
output enable control pins can be selected as
active high or active low. This flexibility not
only allows easy interface with most microproc-
essors, but also eliminates bus contention in
multiple bus microprocessor systems. An addi-
tional feature of the HT23C020 is its ability to
enter the standby mode whenever the chip en-
able (CE/CE or CE1/CE1) is inactive, thus re-
ducing current consumption to below 30µA. The
combination of these functions make the chip
suitable for high density low power memory
applications.
Block Diagram
1 21st Aug ’98
1 page  
A.C. test conditions
Output load: see figure right
Input rise and fall time: 10ns
Input pulse levels: 0.4V to 2.4V
Input and output timing reference levels:
0.8V and 2.0V (VCC=5V), 1.5V (VCC=3V)
HT23C020
Output load circuit
Functional Description
The HT23C020 has two modes, namely data
read mode and standby mode, controlled by
CE/CE/OE1/OE1,CE1/CE1/OE2/OE2/NC and
OE/OE/NC inputs.
• Standby mode
The HT23C020 has lower current consumption,
controlled by the chip enable input (CE/CE and
CE1/CE1). When a low/high level is applied to
the CE/CE or CE1/CE1 input, regardless of the
output enable (OE/OE/NC) states, the chip will
enter the standby mode.
• Data read mode
When both the chip enable (CE/CE/OE1/OE1,
CE1/CE1/OE2/OE2/NC) and the output en-
able (OE/OE/NC) are active, the chip is in
data read mode. Otherwise, active CE/CE,
CE1/CE1 and inactive OE/OE/NC result in
deselect mode. The output will remain in Hi-Z
state.
Timing Diagrams
• Propagation delay due to address (CE/CE/OE1/OE1, CE1/CE1/OE2/OE2
and OE/OE are active)
• Propagation delay due to chip and output enable (address valid)
5 21st Aug ’98
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HT23C020.PDF ] | |
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