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PDF HT16270 Data sheet ( Hoja de datos )
| Número de pieza | HT16270 | |
| Descripción | RAM Mapping 32x4 LCD Controller for I/O C | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HT16270 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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HT16270
RAM Mapping 64 ´16 LCD Controller for I/O mC
Features
· Operating voltage: 2.7V~5.2V
· External Crystal 32.768kHz oscillator
· 1/5 bias, 1/16 duty, frame frequency is 64Hz
· Max. 64´16 patterns, 16 commons,
64 segments
· Built-in internal resistor type bias generator
· 3-wire serial interface
· 8 kinds of time base/WDT selection
· Time base or WDT overflow output
· Built-in LCD display RAM
· R/W address auto increment
· Two selectable buzzer frequencies
(2kHz/4kHz)
· Power down command reduces power
consumption
· Software configuration feature
· Data mode and Command mode instructions
· Three data accessing modes
· VLCD pin to adjust LCD operating voltage
General Description
HT16270 is a peripheral device specially de-
signed for I/O type mC used to expand the dis-
play capability. The max. display segment of
the device are 1024 patterns (64´16). It also
supports serial interface, buzzer sound, watch-
dog timer or time base timer functions. The
HT16270 is a memory mapping and
multi-function LCD controller. The software
configuration feature of the HT16270 make it
suitable for multiple LCD applications includ-
ing LCD modules and display subsystems. Only
three lines are required for the interface be-
tween the host controller and the HT16270.
The HT162X series have many kinds of prod-
ucts that match various applications.
Selection Table
HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
4 4 8 8 8 8 16 16 16
SEG
32 32 32 32 48 64 48 64 64
Built-in Osc.
ÖÖ
ÖÖÖÖ
Crystal Osc. Ö
Ö
Ö ÖÖÖ
Ö
1 April 21, 2000
1 page  
HT16270
Pad Description
Pad No. Pad Name
1 DATA
2 VSS
3 OSCI
4 OSCO
5 VDD
6 VLCD
7 IRQ
8, 9
10~13
14~29
30~93
BZ, BZ
T1~T4
COM0~COM15
SEG0~SEG63
94 CS
95 RD
96 WR
I/O Description
I/O Serial data input/output with pull-high resistor
¾ Negative power supply, ground
I Crystal oscillator input pin
O Crystal oscillato output pin
¾ Positive power supply
I LCD operating voltage input pad.
O
Time base or watchdog timer overflow flag, NMOS open drain
output
O
2kHz or 4kHz tone frequency output pair (Tristate output
buffer)
I Not connected
O LCD common outputs
O LCD segment outputs
Chip selection input with pull-high resistor. When the CS is
logic high, the data and command read from or write to the
I
HT16270 are disabled. The serial interface circuit is also reset.
But if the CS is at logic low level and is input to the CS pad, the
data and command transmission between the host controller
and the HT16270 are all enabled.
READ clock input with pull-high resistor. Data in the RAM of
the HT16270 are clocked out on the rising edge of the RD sig-
I nal. The clocked out data will appear on the data line. The host
controller can use the next falling edge to latch the clocked out
data.
WRITE clock input with pull-high resistor. Data on the DATA
I line are latched into the HT16270 on the rising edge of the WR
signal.
Absolute Maximum Ratings
Supply Voltage .............................-0.3V to 5.5V
Input Voltage .................VSS-0.3V to VDD+0.3V
Storage Temperature.................-50°C to 125°C
Operating Temperature ..............-25°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.
5 April 21, 2000
5 Page 
WRITE mode (command code : 1 0 1)
HT16270
CS
WR
D ATA
1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
WRITE mode (successive address writing)
CS
WR
D ATA
1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
11 April 21, 2000
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HT16270.PDF ] | |
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