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ADC0804 Datasheet PDF - Intersil Corporation

Part Number ADC0804
Description 8-Bit/ Microprocessor- Compatible/ A/D Converters
Manufacturers Intersil Corporation 
Logo Intersil Corporation Logo 

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August 1997
ADC0802, ADC0803
ADC0804
8-Bit, Microprocessor-
Compatible, A/D Converters
Features
Description
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time < 100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required
The ADC0802 family are CMOS 8-Bit, successive-approxi-
mation A/D converters which use a modified potentiometric
ladder and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or I/O ports, and hence no
interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Ordering Information
PART NUMBER
ADC0802LCN
ADC0802LCD
ADC0802LD
ADC0803LCN
ADC0803LCD
ADC0803LCWM
ADC0803LD
ADC0804LCN
ADC0804LCD
ADC0804LCWM
ERROR
±1/2 LSB
±3/4 LSB
±1 LSB
±1/2 LSB
±3/4 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 = 2.500VDC (No Adjustments)
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
PKG. NO
E20.3
F20.3
F20.3
E20.3
F20.3
M20.3
F20.3
E20.3
F20.3
M20.3
Pinout
Typical Application Schematic
ADC0802, ADC0803, ADC0804
(PDIP, CERDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
ANY
µPROCESSOR
1 CS
2 RD
V+ 20
CLK R 19
+5V 150pF
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
VREF/2
DGND
6
7
8
9
10
DIFF
INPUTS
VREF/2
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
6-5
File Number 3094.1

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ADC0804 equivalent
ADC0802, ADC0803, ADC0804
Electrical Specifications (Notes 1, 7) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Logic “1” Output Voltage, VOH lO = -360µA, V+ = 4.75V
2.4 - - V
Three-State Disabled Output
Leakage (All Data Buffers), ILO
VOUT = 0V
VOUT = 5V
-3 -
- µA
- - 3 µA
Output Short Circuit Current,
ISOURCE
VOUT Short to Gnd TA = 25oC
4.5
6
- mA
Output Short Circuit Current,
VOUT Short to V+ TA = 25oC
9.0
16
-
mA
ISINK
NOTES:
1. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the
DGND, being careful to avoid ground loops.
2. For VIN(-) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which
will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful,
during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated tem-
peratures, and cause errors for analog inputs near full scale. As long as the analog VIN does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply volt-
age of 4.950V over temperature variations, initial tolerance and loading.
3. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.
4. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion
process.
5. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse
width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see
Timing Diagrams).
6. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
7. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span
exists (for example: 0.5V to 4V full scale) the VIN(-) input can be adjusted to achieve this. See the Zero Error description in this data sheet.
Timing Waveforms
V+
RD
CS
DATA
OUTPUT
CL 10K
FIGURE 1A. t1H
2.4V
RD
0.8V
tr = 20ns
tr
90%
50%
10%
VOH
DATA
OUTPUTS
GND
t1H
90%
FIGURE 1B. t1H, CL = 10pF
V+ V+
10K
RD DATA
CS OUTPUT
CL
FIGURE 1C. t0H
2.4V
RD
0.8V
tr = 20ns
tr
90%
50%
10%
t0H
V+
DATA
OUTPUTS
VOI
10%
FIGURE 1D. t0H, CL = 10pF
FIGURE 1. THREE-STATE CIRCUITS AND WAVEFORMS
6-9


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1. 8-bit A/D Converter - Intersil

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